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AD684JQ bảng dữ liệu(PDF) 6 Page - Analog Devices |
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AD684JQ bảng dữ liệu(HTML) 6 Page - Analog Devices |
6 / 8 page AD684 REV. A –6– OP484 DYNAMIC PERFORMANCE The AD684 is compatible with 12-bit A-to-D converters in terms of both accuracy and speed. The fast acquisition time, fast hold settling time and good output drive capability allow the AD684 to be used with high speed, high resolution A-to-D converters like the AD674 and AD7672. The AD684’s fast acquisition time provides high throughput rates for multichannel data acquisition systems. Typically, the sample and hold can acquire a 10 V step in less than 750 ns. Figure 1 shows the settling accuracy as a function of acquisition time. Figure 1. VOUT Settling vs. Acquisition Time The hold settling determines the required time, after the hold command is given, for the output to settle to its final specified accuracy. The typical settling behavior of the AD684 is shown in Figure 2. The settling time of the AD684 is sufficiently fast to allow the SHA, in most cases, to directly drive an A-to-D converter without the need for an added “start convert” delay. Figure 2. Typical AD684 Hold Mode HOLD MODE OFFSET The dc accuracy of the AD684 is determined primarily by the hold mode offset. The hold mode offset refers to the difference between the final held output voltage and the input signal at the time the hold command is given. The hold mode offset arises from a voltage error introduced onto the hold capacitor by charge injec- tion of the internal switches. The nominal hold mode offset is specified for a 0 V input condition. Over the input range of –5 V to +5 V, the AD684 is also characterized for an effective gain error and nonlinearity of the held value, as shown in Figure 3. As indicated by the AD684 specifications, the hold mode offset is very well matched between channels and stable over temperature. Figure 3. Hold Mode Offset, Gain Error and Nonlinearity For applications where it is important to obtain zero offset, the hold mode offset may be nulled externally at the input to the A-to-D converter. Adjustment of the offset may be accom- plished through the A-to-D itself or by an external amplifier with offset nulling capability (e.g., AD711). Only a single adjustment of the offset is necessary for the four SHA channels as a result of the excellent matching among them. The offset will change less than 0.5 mV over the specified temperature range. SUPPLY DECOUPLING AND GROUNDING CONSIDERATIONS As with any high speed, high resolution data acquisition system, the power supplies should be well regulated and free from excessive high frequency noise (ripple). The supply connection to the AD684 should also be capable of delivering transient currents to the device. To achieve the specified accuracy and dynamic performance, decoupling capacitors must be placed directly at both the positive and negative supply pins to common. Ceramic type 0.1 µF capacitors should be connected from V CC and VEE to common. Figure 4. Basic Grounding and Decoupling Diagram |
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