công cụ tìm kiếm bảng dữ liệu linh kiện điện tử
  Vietnamese  ▼
ALLDATASHEET.VN

X  

AD671JD-750 bảng dữ liệu(PDF) 10 Page - Analog Devices

tên linh kiện AD671JD-750
Giải thích chi tiết về linh kiện  Monolithic 12-Bit 2 MHz A/D Converter
Download  16 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
nhà sản xuất  AD [Analog Devices]
Trang chủ  http://www.analog.com
Logo AD - Analog Devices

AD671JD-750 bảng dữ liệu(HTML) 10 Page - Analog Devices

Back Button AD671JD-750 Datasheet HTML 6Page - Analog Devices AD671JD-750 Datasheet HTML 7Page - Analog Devices AD671JD-750 Datasheet HTML 8Page - Analog Devices AD671JD-750 Datasheet HTML 9Page - Analog Devices AD671JD-750 Datasheet HTML 10Page - Analog Devices AD671JD-750 Datasheet HTML 11Page - Analog Devices AD671JD-750 Datasheet HTML 12Page - Analog Devices AD671JD-750 Datasheet HTML 13Page - Analog Devices AD671JD-750 Datasheet HTML 14Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 16 page
background image
AD671
REV. B
–10–
it should be trimmed as above, although a different offset can be
set for a particular system requirement. This circuit will give ap-
proximately
±50 mV of offset trim range.
The gain trim is done by applying a signal 1 1/2 LSBs below the
nominal full scale (9.9963 for a 10 V range). Trim R1 to give
the last transition (1111 1111 1110 to 11111111 1111).
UNIPOLAR (0 V TO +5 V) CALIBRATION
The connections for the 0 V to +5 V input range calibration is
shown in Figure 8. The AD586, a +5 V precision voltage refer-
ence, is an excellent choice for this mode of operation because
of its performance, stability and optional fine trim. The AD845
(16 MHz, low power, low cost op amp) is used to maintain the
+5 volts under the dynamically changing load conditions of the
reference input.
AD845
AIN
REFIN
BPO/UPO
ACOM
BIT1
BIT12
DCOM
AD671
ENCODE
DAV
OTR
MSB
6
7
2
3
4
20
23
24
17
22
18
19
21
13
14
15
16
V
CC
V
EE
V
LOGIC
1
12
AD845
6
7
2
3
4
6
5
4
8
2
+V
IN
+15V
V
OUT
TRIM
GND
NOISE
REDUCTION
AD586
1
µF
8
1
+15V
0.1
µF
390
+15V
–15V
0.1
µF
0 TO +5V
–15V
0.1
µF
+15V
0.1
µF
10k
1k
Figure 8. Unipolar (0 V to +5 V) Calibration
The AD671 offset error must be trimmed within the analog in-
put path, either directly in front of the AD671 or within the sig-
nal conditioning chain, eliminating offset errors induced by the
signal conditioning circuitry. Figure 8 shows an example of how
the offset error can be trimmed in front of the AD671. The
AD586 is configured in the optional fine trim mode to provide
+6%/–2% (+240 LSBs/–80 LSBs) of gain trim. The procedure
for trimming the offset and gain errors is similar to that used for
the unipolar 10 V range with the analog input values set to one-
half the 10 V range values.
BIPOLAR ( 5 V) CALIBRATION
The connections for the bipolar input range is shown in Figure
9. The AD588 is configured to provide dual +5 V outputs. Pro-
viding a +5 V reference voltage for the AD671 gain trim and the
+5 V BPO/UPO input for the bipolar offset trim.
AIN
REF IN
BPO/UPO
ACOM
BIT1
BIT12
DCOM
AD671
ENCODE
DAV
OTR
MSB
20
23
24
17
22
18
19
21
13
14
15
16
V
CC
V
EE
V
LOGIC
1
12
±5V
0.1
µF
10
µF
0.1
µF
10
µF
1
14
15
50
150pF
50
13
12
11
8
10
9
5
7
6
4
3
1
µF
AD588
150pF
R2
100
39k
15V
+
2
16
+15
–15
R1
100
6.2k
Figure 9. Bipolar (
±5 V) Calibration
Bipolar calibration is similar to unipolar calibration. First, a sig-
nal 1/2 LSB above negative full scale (–4.9988 V) is applied and
R1 is trimmed to give the first transition (0000 0000 0000 to
0000 0000 0001). Then a signal 1 1/2 LSB below positive full
scale (+4.9963) is applied, and R2 is trimmed to give the last
transition (1111 1111 1110 to 1111 1111 1111).
OUTPUT LATCHES
Figure 10 shows the AD671 connected to the 74HC574 Octal
D-type edge triggered latches with 3-state outputs. The latch
can drive highly capacitive loads (i.e., bus lines, I/O ports) while
maintaining the data signal integrity. The maximum set-up and
hold times of the 574 type latch must be less than 20 ns (tDD
and tSS minimum). To satisfy the requirements of the 574 type
latch the recommended logic families are HC, S, AS, ALS, F or
BCT. New data from the AD671 is latched on the rising edge of
the DAV (Pin 24) output pulse. Previous data can be latched by
inverting the DAV output with a 7404 type inverter. See Fig-
ures 20, 21 and 22 for PCB layout recommendations.
1D
2D
3D
4D
5D
6D
7D
8D
CLK
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
1D
2D
3D
4D
5D
6D
7D
8D
CLK
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
BIT8
BIT9
BIT10
BIT11
BIT12
DAV
DATA BUS
3-STATE
CONTROL
AD671
OC
OC
74HC574
74HC574
U6
U5
Figure 10. AD671 to Output Latches
OUT OF RANGE
An Out of Range condition exists when the analog input voltage
is beyond the input range (0 V to +5 V, 0 V to +10 V,
±5 V) of
the converter. OTR (Pin 14) is set low when the analog input
voltage is within the analog input range. OTR is set HIGH and
will remain HIGH when the analog input voltage exceeds the
input range by typically 1/2 LSB (OTR transition is tested to
±6 LSBs of accuracy) from the center of the ± full-scale output
codes. OTR will remain HIGH until the analog input is within
the input range and another conversion is completed. By logical
ANDing OTR with the MSB and its complement overrange
high or underrange low conditions can be detected. Table II is a
truth table for the over/under range circuit in Figure 11. Sys-
tems requiring programmable gain conditioning prior to the
AD671 can immediately detect an out of range condition, thus
eliminating gain selection iterations.
Table II. Out of Range Truth Table
OTR
MSB
Analog Input Is
0
0
In Range
0
1
In Range
1
0
Underrange
1
1
Overrange


Số phần tương tự - AD671JD-750

nhà sản xuấttên linh kiệnbảng dữ liệuGiải thích chi tiết về linh kiện
logo
Analog Devices
AD671 AD-AD671_15 Datasheet
389Kb / 16P
   Monolithic 12-Bit 2 MHz A/D Converter
REV. B
More results

Mô tả tương tự - AD671JD-750

nhà sản xuấttên linh kiệnbảng dữ liệuGiải thích chi tiết về linh kiện
logo
Analog Devices
AD671 AD-AD671_15 Datasheet
389Kb / 16P
   Monolithic 12-Bit 2 MHz A/D Converter
REV. B
AD9022 AD-AD9022_15 Datasheet
411Kb / 12P
   12-Bit 20 MSPS Monolithic A/D Converter
REV. A
AD568 AD-AD568_15 Datasheet
544Kb / 14P
   12-Bit Ultrahigh Speed Monolithic D/A Converter
REV. A
AD9022 AD-AD9022 Datasheet
240Kb / 12P
   12-Bit 20 MSPS Monolithic A/D Converter
REV. B
AD9042 AD-AD9042 Datasheet
488Kb / 24P
   12-Bit, 41 MSPS Monolithic A/D Converter
REV. A
AD568 AD-AD568 Datasheet
541Kb / 14P
   12-Bit Ultrahigh Speed Monolithic D/A Converter
REV. A
logo
National Semiconductor ...
CLC5957 NSC-CLC5957 Datasheet
631Kb / 12P
   12-bit, 70MSPS Broadband Monolithic A/D Converter
logo
Renesas Technology Corp
HI-DAC80V RENESAS-HI-DAC80V Datasheet
483Kb / 8P
   12-Bit, Low Cost, Monolithic D/A Converter
logo
Analog Devices
AD6012 AD-AD6012_15 Datasheet
2Mb / 6P
   LOW COST MONOLITHIC 12 BIT D/A CONVERTER
logo
Intersil Corporation
HI-DAC80V INTERSIL-HI-DAC80V_01 Datasheet
92Kb / 8P
   12-Bit, Low Cost, Monolithic D/A Converter
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16


bảng dữ liệu tải về

Go To PDF Page


Link URL




Chính sách bảo mật
ALLDATASHEET.VN
Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không?  [ DONATE ] 

Alldatasheet là   |   Quảng cáo   |   Liên lạc với chúng tôi   |   Chính sách bảo mật   |   Trao đổi link   |   Tìm kiếm theo nhà sản xuất
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com