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AD568S bảng dữ liệu(PDF) 10 Page - Analog Devices |
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AD568S bảng dữ liệu(HTML) 10 Page - Analog Devices |
10 / 14 page AD568 REV. A –10– Circuit layout for a high speed SHA is almost as critical as the design itself. Figure 17 shows a recommended layout of the deglitching cell for a double sided printed circuit board. The layout is very compact with care taken that all critical signal paths are short. –5V MC 10124 249 Ω 169 Ω 510 Ω 360 Ω 360 Ω –5V 169 Ω 249 Ω 500pF OUTPUT 75 Ω 200 Ω 200 Ω IN4735 +15V –15V –15V 20k Ω 1.6 Ω 0.39µF TO PIN 2 SD5000 100pF 4 5 10 11 9 16 14 13 12 6 8 5 4 3 1 AD841 Figure 17. High Performance Deglitcher Grounding Rules The AD568 brings out separate reference, output, and digital power grounds. This allows for optimum management of signal ground currents for low noise and high-speed-settling perfor- mance. The separate ground returns are provided to minimize changes in current flow in the analog signal paths. In this way, logic return currents are not summed into the same return path with the analog signals. It is important to understand which supply and signal currents are flowing in which grounds so that they may be returned to the proper power supply in the best possible way. The majority of the current that flows into the VCC supply (Pin 24) flows out (depending on the DAC input code) either the ANALOG COMMON (Pin 18), the LADDER COMMON (Pin 17), and/or IOUT (Pin 20). The current in the LADDER COMMON is configured to be code independent when the output current is being summed into a virtual ground. If IOUT is operated into its own output im- pedance (or in any unbuffered voltage output mode) the current in LADDER COMMON will become partially code dependent. The current in the ANALOG COMMON (Pin 18) is an ap- proximate complement of the current in IOUT, i.e., zero when the DAC is at full scale and approximately 10 mA at zero input code. A relatively constant current (not code dependent) flows out the REFERENCE COMMON (Pin 23). The current flowing out of the VEE supply (Pin 22) comes from a combination of reference ground and BIPOLAR OFFSET (Pin 21). The plus and minus 15 V supplies are decoupled to the REFERENCE COMMON. The ground side of the load resistor RL, ANALOG COMMON and LADDER COMMON should be tied together as close to the package pins as possible. The analog output voltage is then referred to this node and thus it becomes the “high quality” ground for the AD568. The REFERENCE COMMON (and Bipolar offset when not used), should also be connected to this node. All of the current that flows into the VTH terminal (Pin 13) from the resistor tied to the 5 V logic supply (or other convenient positive supply) flows out the THRESHOLD COMMON (Pin 14). This ground pin should be returned directly to the digital ground plane on its own individual line. The +5 V logic supply should be decoupled to the THRESH- OLD COMMON. Because the VTH pin is connected directly to the DAC switches it should be decoupled to the analog output signal common. In order to preserve proper operation of the DAC switches, the digital and analog grounds need to eventually be tied together. This connection between the ground planes should be made within 1/2" of the DAC. The Use of Ground and Power Planes If used properly, ground planes can perform a myriad of func- tions on high-speed circuit boards: bypassing, shielding, current transport, etc. In mixed signal design, the analog and digital por- tions of the board should be distinct from one another, with the analog ground plane covering analog signal traces and the digital ground plane confined to areas covering digital interconnect. The two ground planes should be connected at or near the DAC. Care should be taken to insure that the ground plane is uninterrupted over crucial signal paths. On the digital side, this includes the digital input lines running to the DAC and any clock lines. On the analog side, this incudes the DAC output signal as well as the supply feeders. The use of side runs or planes in the routing of power lines is also recommended. This serves the dual function of providing a low series impedance power supply to the part as well as providing some ‘‘free’’ ca- pacitive decoupling to the appropriate ground plane. Figure 18 illustrates many of the points discussed above. If more layers of interconnect are available, even better results are possible. Using the Right Bypass Capacitors Probably the most important external components associated with any high-speed design are the capacitors used to bypass the power supplies. Both selection and placement of these ca- pacitors can be critical and, to a large extent, dependent upon the specifics of the system configurations. The dominant consid- eration in selection of bypass capacitors for the AD568 is mini- mization of series resistance and inductance. Many capacitors will begin to look inductive at 20 MHz and above, the very fre- quencies we are most interested in bypassing. Ceramic and film- type capacitors generally feature lower series inductance than tantalum or electrolytic types. A few general rules are of univer- sal use when approaching the problem of bypassing: Bypass capacitors should be installed on the printed circuit board with the shortest possible leads consistent with reliable construction. This helps to minimize series inductance in the leads. Chip capacitors are optimal in this respect. Some series inductance between the DAC supply pins and the power supply plane often helps to filter out high-frequency power supply noise. This inductance can be generated using a small ferrite bead. |
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