AD5551/AD5552

–9–

REV. 0

The AD5552 has an

LDAC function that allows the DAC latch

to be updated asynchronously by bringing

LDAC low after CS

goes high.

LDAC should be maintained high while data is written

to the shift register. Alternatively,

LDAC may be tied permanently

low to update the DAC synchronously. With

LDAC tied perma-

nently low, the rising edge of

CS will load the data to the DAC.

Unipolar Output Operation

These DACs are capable of driving unbuffered loads of 60 k

Ω.

Unbuffered operation results in low-supply current, typically

300

µA, and a low-offset error. The AD5551 provides a unipolar

configured to output both unipolar and bipolar voltages. Fig-

ure 3 shows a typical unipolar output voltage circuit. The code

table for this mode of operation is shown in Table I.

AD5551/AD5552

AD820/

OP196

DGND

OUT

SCLK

DIN

CS

AGND

5V

2.5V

EXTERNAL

OP AMP

UNIPOLAR

OUTPUT

10 F

0.1 F

0.1 F

SERIAL

INTERFACE

Figure 3. Unipolar Output

Table I. Unipolar Code Table

DAC Latch Contents

MSB

LSB

Analog Output

11 1111 1111 1111

× (16383/16384)

10 0000 0000 0000

× (8192/16384) = 1/2 V

REF

00 0000 0000 0001

× (1/16384)

00 0000 0000 0000

0 V

Assuming a perfect reference, the worst-case output voltage may

be calculated from the following equation.

Unipolar Mode Worst-Case Output

V

D

V

V

V

INL

OUT UNI

REF

GE

ZSE

–

()

=×

+

+

+

2

14

where

D

= Decimal Code Loaded to DAC

= Reference Voltage Applied to Part

= Gain Error in Volts

= Zero Scale Error in Volts

INL

= Integral Nonlinearity in Volts

Bipolar Output Operation

With the aid of an external op amp, the AD5552 may be config-

ured to provide a bipolar voltage output. A typical circuit of

such operation is shown in Figure 4. The matched bipolar offset

Ω.

Table II shows the transfer function for this output operating

mode. Also provided on the AD5552 are a set of Kelvin connec-

tions to the analog ground inputs.

AD5551/AD5552

DGND

OUT

SCLK

DIN

CS

5V

2.5V

EXTERNAL

OP AMP

BIPOLAR

OUTPUT

10 F

SERIAL

INTERFACE

0.1 F

LDAC

0.1 F

INV

+5V

–5V

RFB

AGNDS

AGNDF

Figure 4. Bipolar Output (AD5552 Only)

Table II. Bipolar Code Table

DAC Latch Contents

MSB

LSB

Analog Output

11 1111 1111 1111

× (8191/8192)

10 0000 0000 0000

× (1/8192)

00 0000 0000 0001

0 V

00 0000 0000 0000

× (1/8192)

00 0000 0000 0000

Assuming a perfect reference, the worst-case bipolar output

voltage may be calculated from the following equation.

Bipolar Mode Worst-Case Output

V

VV

RD

V

RD

RD A

OUT BIP

OUT UNI

OS

REF

–

–

–

/

=

+

()

+

()

[]

++

()

21

12

where

A

= Op Amp Open-Loop Gain

Output Amplifier Selection

For bipolar mode, a precision amplifier should be used, supplied

from a dual power supply. This will provide the

In a single-supply application, selection of a suitable op amp

may be more difficult as the output swing of the amplifier does

not usually include the negative rail, in this case AGND. This

can result in some degradation of the specified performance

unless the application does not use codes near zero.

The selected op amp needs to have very low-offset voltage, (the

DAC LSB is 152

µV with a 2.5 V reference), to eliminate the

need for output offset trims. Input bias current should also be

very low as the bias current multiplied by the DAC output

impedance (approximately 6K) will add to the zero code error.

Rail-to-rail input and output performance is required. For fast

settling, the slew rate of the op amp should not impede the

settling time of the DAC. Output impedance of the DAC is

constant and code-independent, but in order to minimize gain

errors, the input impedance of the output amplifier should be

as high as possible. The amplifier should also have a 3 dB band-

width of 1 MHz or greater. The amplifier adds another time

constant to the system, hence increasing the settling time of the

output. A higher 3 dB amplifier bandwidth results in a faster

effective settling time of the combined DAC and amplifier.