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AD5544ARS bảng dữ liệu(PDF) 8 Page - Analog Devices |
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AD5544ARS bảng dữ liệu(HTML) 8 Page - Analog Devices |
8 / 16 page REV. 0 AD5544/AD5554 –8– AD5544/AD5554 PIN FUNCTION DESCRIPTIONS Pin # Name Function 1AGNDA DAC A Analog Ground. 2IOUTA DAC A Current Output. 3VREFA DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can be tied to VDD pin. 4RFBA Establish Voltage Output for DAC A by Connecting to External Amplifier Output. 5 MSB MSB Bit Set Pin During a Reset Pulse ( RS) or at System Power ON if Tied to Ground or V DD. 6 RS Reset Pin, Active Low Input. Input registers and DAC registers are set to all zeros or half-scale code (8000H for AD5544 and 2000H for AD5554) determined by the voltage on the MSB pin. Register Data = 0000H when MSB = 0. Register Data = 8000H for AD5544 and 2000H for AD5554 when MSB = 1. 7VDD Positive Power Supply Input. Specified range of operation 5 V ± 10%. 8 CS Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register data to the Input Register when CS/LDAC returns High. Does not effect LDAC operation. 9 CLK Clock Input, Positive Edge Clocks Data into Shift Register. 10 SDI Serial Data Input, Input Data Loads Directly into the Shift Register. 11 RFBB Establish Voltage Output for DAC B by Connecting to External Amplifier Output. 12 VREFB DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. Pin can be tied to VDD pin. 13 IOUTB DAC B Current Output. 14 AGNDB DAC B Analog Ground. 15 AGNDC DAC C Analog Ground. 16 IOUTC DAC C Current Output. 17 VREFC DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. Pin can be tied to VDD pin. 18 RFBC Establish voltage output for DAC C by connecting to external amplifier output. 19 NC No Connect. Leave pin unconnected. 20 SDO Serial Data Output, input data loads directly into the shift register. Data appears at SDO, 19 clock pulses for AD5544 and 17 clock pulses for AD5554 after input at the SDI pin. 21 LDAC Load DAC Register Strobe, Level Sensitive Active Low. Transfers all Input Register data to DAC registers. Asyn- chronous active low input. See Control Logic Truth Table for operation. 22 AGNDF High Current Analog Force Ground. 23 VSS Negative Bias Power Supply Input. Specified range of operation –0.3 V to –5.5 V. 24 DGND Digital Ground Pin. 25 RFBD Establish Voltage Output for DAC D by Connecting to External Amplifier Output. 26 VREFD DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. Pin can be tied to VDD pin. 27 IOUTD DAC D Current Output. 28 AGNDD DAC D Analog Ground. AD5544/AD5554 PIN CONFIGURATION TOP VIEW (Not to Scale) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AD5544/ AD5554 AGNDAAGNDD IOUTAIOUTD VREFAVREFD RFBARFBD MSB DGND RS VSS VDD AGNDF CS LDAC CLK SDO SDI NC RFBBRFBC VREFBVREFC IOUTBIOUTC AGNDBAGNDC NC = NO CONNECT |
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