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AD5541LR bảng dữ liệu(PDF) 10 Page - Analog Devices |
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10 / 12 page AD5541/AD5542 –10– REV. A The AD5542 has an LDAC function that allows the DAC latch to be updated asynchronously by bringing LDAC low after CS goes high. LDAC should be maintained high while data is written to the shift register. Alternatively, LDAC may be tied permanently low to update the DAC synchronously. With LDAC tied perma- nently low, the rising edge of CS will load the data to the DAC. Unipolar Output Operation These DACs are capable of driving unbuffered loads of 60 k Ω. Unbuffered operation results in low-supply current, typically 300 µA, and a low-offset error. The AD5541 provides a unipolar output swing ranging from 0 V to VREF. The AD5542 can be configured to output both unipolar and bipolar voltages. Figure 19 shows a typical unipolar output voltage circuit. The code table for this mode of operation is shown in Table I. AD5541/AD5542 AD820/ OP196 DGND * AD5542 ONLY VDD REFS* REF(REFF*) OUT SCLK DIN CS AGND +5V +2.5V EXTERNAL OP AMP UNIPOLAR OUTPUT 10 F 0.1 F LDAC* 0.1 F SERIAL INTERFACE Figure 19. Unipolar Output Table I. Unipolar Code Table DAC Latch Contents MSB LSB Analog Output 1111 1111 1111 1111 VREF × (65,535/65,536) 1000 0000 0000 0000 VREF × (32,768/65,536) = 1/2 VREF 0000 0000 0000 0001 VREF × (1/65,536) 0000 0000 0000 0000 0 V Assuming a perfect reference, the worst case output voltage may be calculated from the following equation. Unipolar Mode Worst-Case Output V D V V V INL OUT UNI REF GE ZSE – () = × +++ 216 where VOUT–UNI = Unipolar Mode Worst-Case Output D = Code Loaded to DAC VREF = Reference Voltage Applied to Part VGE = Gain Error in Volts VZSE = Zero Scale Error in Volts INL = Integral Nonlinearity in Volts Bipolar Output Operation With the aid of an external op amp, the AD5542 may be config- ured to provide a bipolar voltage output. A typical circuit of such operation is shown in Figure 20. The matched bipolar off- set resistors RFB and RINV are connected to an external op amp to achieve this bipolar output swing, typically RFB = RINV = 28 kΩ. Table II shows the transfer function for this output operating mode. Also provided on the AD5542 are a set of Kelvin connec- tions to the analog ground inputs. AD5541/AD5542 DGND VDD REFS REFF OUT SCLK DIN CS +5V +2.5V EXTERNAL OP AMP BIPOLAR OUTPUT 10 F SERIAL INTERFACE 0.1 F LDAC 0.1 F INV RINV +5V –5V RFB RFB AGNDS AGNDF Figure 20. Bipolar Output (AD5542 Only) Table II. Bipolar Code Table DAC Latch Contents MSB LSB Analog Output 1111 1111 1111 1111 +VREF × (32,767/32,768) 1000 0000 0000 0001 +VREF × (1/32,768) 1000 0000 0000 0000 0 V 0111 1111 1111 1111 –VREF × (1/32,768) 0000 0000 0000 0000 –VREF × (32,768/32,768) = –VREF Assuming a perfect reference, the worst-case bipolar output voltage may be calculated from the following equation. Bipolar Mode Worst-Case Output V VV RD V RD RD A OUT BIP OUT UNI OS REF – – – / = + () + () + () [] ++ () 21 12 where VOS = External Op Amp Input Offset Voltage RD = RFB and RIN Resistor Matching Error A = Op Amp Open-Loop Gain Output Amplifier Selection For bipolar mode, a precision amplifier should be used, supplied from a dual power supply. This will provide the ±V REF output. In a single-supply application, selection of a suitable op amp may be more difficult as the output swing of the amplifier does not usually include the negative rail, in this case AGND. This can result in some degradation of the specified performance unless the application does not use codes near zero. The selected op amp needs to have very low-offset voltage, (the DAC LSB is 38 µV with a 2.5 V reference), to eliminate the need for output offset trims. Input bias current should also be very low as the bias current multiplied by the DAC output impedance (approximately 6K) will add to the zero code error. Rail-to-rail input and output performance is required. For fast settling, the slew rate of the op amp should not impede the settling time of the DAC. Output impedance of the DAC is constant and code-independent, but in order to minimize gain errors, the input impedance of the output amplifier should be as high as possible. The amplifier should also have a 3 dB band- width of 1 MHz or greater. The amplifier adds another time constant to the system, hence increasing the settling time of the output. A higher 3 dB amplifier bandwidth results in a shorter effective settling time of the combined DAC and amplifier. Force Sense Amplifier Selection These amplifiers will be single-supply, low-noise amplifiers. A low-output impedance at high frequencies is preferred as they need to be able to handle dynamic currents of up to ±20 mA. |
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