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AD5322 bảng dữ liệu(PDF) 2 Page - Analog Devices

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Giải thích chi tiết về linh kiện  2.5 V to 5.5 V, 115 uA, Parallel Interface Single Voltage-Output 8-/10-/12-Bit DACs
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AD5322 bảng dữ liệu(HTML) 2 Page - Analog Devices

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REV. 0
–2–
AD5330/AD5331/AD5340/AD5341–SPECIFICATIONS
(VDD = 2.5 V to 5.5 V, VREF = 2 V. RL = 2 k
to GND; CL = 200 pF to GND; all specifications TMIN to TMAX unless otherwise noted.)
B Version
2
Parameter
1
Min
Typ
Max
Unit
Conditions/Comments
DC PERFORMANCE
3, 4
AD5330
Resolution
8
Bits
Relative Accuracy
±0.15
±1
LSB
Differential Nonlinearity
±0.02
±0.25
LSB
Guaranteed Monotonic By Design Over All Codes
AD5331
Resolution
10
Bits
Relative Accuracy
±0.5
±4
LSB
Differential Nonlinearity
±0.05
±0.5
LSB
Guaranteed Monotonic By Design Over All Codes
AD5340/AD5341
Resolution
12
Bits
Relative Accuracy
±2
±16
LSB
Differential Nonlinearity
±0.2
±1
LSB
Guaranteed Monotonic By Design Over All Codes
Offset Error
±0.4
±3
% of FSR
Gain Error
±0.15
±1
% of FSR
Lower Deadband
5
10
60
mV
Lower Deadband Exists Only if Offset Error Is Negative
Upper Deadband
10
60
mV
VDD = 5 V. Upper Deadband Exists Only if VREF = VDD
Offset Error Drift6
–12
ppm of FSR/
°C
Gain Error Drift
6
–5
ppm of FSR/
°C
DC Power Supply Rejection Ratio
6
–60
dB
∆VDD = ±10%
DAC REFERENCE INPUT
6
VREF Input Range
1
VDD
V
Buffered Reference (AD5330, AD5340, and AD5341)
0.25
VDD
V
Unbuffered Reference
VREF Input Impedance
>10
M
Buffered Reference (AD5330, AD5340, and AD5341)
180
k
Unbuffered Reference. Gain = 1, Input Impedance = RDAC
90
k
Unbuffered Reference. Gain = 2, Input Impedance = RDAC
Reference Feedthrough
–90
dB
Frequency = 10 kHz
OUTPUT CHARACTERISTICS
6
Minimum Output Voltage
4, 7
0.001
V min
Rail-to-Rail Operation
Maximum Output Voltage
4, 7
VDD–0.001
V max
DC Output Impedance
0.5
Short Circuit Current
25
mA
VDD = 5 V
15
mA
VDD = 3 V
Power-Up Time
2.5
µs
Coming Out of Power-Down Mode. VDD = 5 V
5
µs
Coming Out of Power-Down Mode. VDD = 3 V
LOGIC INPUTS
6
Input Current
±1
µA
VIL, Input Low Voltage
0.8
V
VDD = 5 V
± 10%
0.6
V
VDD = 3 V
± 10%
0.5
V
VDD = 2.5 V
VIH, Input High Voltage
2.4
V
VDD = 5 V
± 10%
2.1
V
VDD = 3 V
± 10%
2.0
V
VDD = 2.5 V
Pin Capacitance
3
pF
POWER REQUIREMENTS
VDD
2.5
5.5
V
IDD (Normal Mode)
DACs active and excluding load currents. Unbuffered
VDD = 4.5 V to 5.5 V
140
250
µA
Reference. VIH = VDD, VIL = GND.
VDD = 2.5 V to 3.6 V
115
200
µAIDD increases by 50 µA at VREF > VDD – 100 mV.
In Buffered Mode extra current is (5 + VREF/RDAC)
µA,
where RDAC is the resistance of the resistor string.
IDD (Power-Down Mode)
VDD = 4.5 V to 5.5 V
0.2
1
µA
VDD = 2.5 V to 3.6 V
0.08
1
µA
NOTES
1See Terminology section.
2Temperature range: B Version: –40
°C to +105°C; typical specifications are at 25°C.
3Linearity is tested using a reduced code range: AD5330 (Code 8 to 255); AD5331 (Code 28 to 1023); AD5340/AD5341 (Code 115 to 4095).
4DC specifications tested with output unloaded.
5This corresponds to x codes. x = Deadband voltage/LSB size.
6Guaranteed by design and characterization, not production tested.
7In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, V
REF = VDD and
“Offset plus Gain” Error must be positive.
Specifications subject to change without notice.


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