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AD53513JSQ bảng dữ liệu(PDF) 2 Page - Analog Devices |
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AD53513JSQ bảng dữ liệu(HTML) 2 Page - Analog Devices |
2 / 4 page –2– REV. 0 AD53513–SPECIFICATIONS (All specifications are at TJ = 85 C 5 C, +VS = +9 V 3%, –VS = –6 V 3% unless otherwise noted. All temperature coefficients are measured at TJ = 75 C–95 C). (A 39 nF capacitor must be connected between VCC and VHDCPL and between VEE and VLDCPL.) Parameter Min Typ * Max Unit Test Conditions DIFFERENTIAL INPUT CHARACTERISTICS (Data to DATA, INH to INH), RLD, VBB VBB = –1.3 V Input Voltage –2 0 Volts Differential Input Range ECL Bias Current –1 +1 mA VIN = –2 V, 0.0 V VBB Threshold Input Midrange V Set to Midrange of Logic Levels REFERENCE INPUTS (VL, VH, VT) Bias Currents –50 +50 µAV L, VH = 2 V OUTPUT CHARACTERISTICS Logic High Range –2.3 +5.5 Volts DATA = H Logic Low Range –2.5 +5.3 Volts DATA = L Amplitude (VH–VL) 0.2 8.0 Volts Absolute Accuracy VH Offset –100 +100 mV DATA = H, VH = 0 V, VL = –2 V, VT = +3 V VH Gain and Linearity Error ±0.3 ±5% of V H + mV DATA = H, VH = –2 V to +5 V, VL = –2.5 V, VT = +3 V VL Offset –100 +100 mV DATA = L, VL = 0 V, VH = +5 V, VT = +4.5 V VL Gain and Linearity Error ±0.3 ±5% of V L + mV DATA = L, VL = –2 V to +5 V, VH = +5.5 V, VT = +4.5 V VT Offset –100 +100 mV Term Mode, VT = 0 V, VL = –1 V, VH = +3 V VT Gain and Linearity Error ±0.3 ±5% of V T + mV Term Mode, VT = –2.0 V to +5.0 V, VL = 0, VH = +3 V Offset TC, VH, or VL, or VTERM ±0.5 mV/ °CV L, VH = 0 V Output Resistance 20 Ω DATA = H, VH = 3 V, VL = 0 V, IOUT = 45 mA Output Leakage –1.0 +1.0 µAV OUT = –2 V to +5 V Dynamic Current Limit 130 mA CBYP = 39 nF, VH = +5 V, VL = –2 V Static Current Limit ±85 mA Output to –2.5 V, VH = +5.5 V, VL = –2.5 V, VT = 0; DATA = H and Output to 5.5 V, VH = +5.5 V, VL = –2.5 V, VT = 0 VL = –3 V, DATA = L PSRR, Drive Mode 35 dB VS = VS ± 3% DYNAMIC PERFORMANCE, DRIVE (VH and VL) Propagation Delay Time 0.3 1.1 ns Measured at 50%, VH = 800 mV, 50 Ω Load, VL = –800 mV Propagation Delay TC ±0.5 ps/ °C Measured at 50%, VH = 800 mV, 50 Ω Load, VL = –800 mV Delay Matching, Edge to Edge 100 ps Measured at 50%, VH = 800 mV, 50 Ω Load, VL = –800 mV Rise and Fall Time 1 V Swing 300 ps Measured 20%–80%, VL = 0 V, VH = 1 V, VT = –2 V 2 V Swing 450 ps Measured 10%–90%, VL = 0 V, VH = 2 V, VT = –2 V 3 V Swing 650 ps Measured 10%–90%, VL = 0 V, VH = 3 V, VT = –2 V Rise and Fall Time TC 1 V Swing ±1 ps/ °C Measured 20%–80%, VL = 0 V, VH = 1 V, VT = –2 V 2 V Swing ±1 ps/ °C Measured 10%–90%, VL = 0 V, VH = 2 V, VT = –2 V 3 V Swing ±1 ps/ °C Measured 10%–90%, VL = 0 V, VH = 3 V, VT = –2 V Overshoot, Undershoot, and Preshoot ±(6% +50 mV) % of Step + mV a. VL, VH = 0 V, +1 V, VT = –2 V, 50 Ω b. VL, VH = 0 V, +3 V, VT = –2 V, 50 Ω c. VL, VH = 0 V, +5 V, VT = –2 V, 50 Ω Settling Time to 15 mV 50 ns VL = 0 V, VH = +0.5 V, VT = –2 V to 4 mV 10 µsV L = 0 V, VH = +0.5 V, VT = –2 V Delay Change vs. Pulsewidth 10 ps VL = 0 V, VH = +2 V, VT = –2 V, Pulsewidth/Period = 1.0 ns/4.0 ns, 30 ns/120 ns Minimum Pulsewidth 2 V Swing 700 ps 700 ps Input, 10%/90% Output, VT = –2 V, VL = 0 V, VH = +2 V, 50 Ω Terminated Toggle Rate 3.2 GHz VL = –1.8 V, VH = –0.8 V, VT = –2 V, VOUT > 300 mV p-p at 50 Ω Terminated |
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