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AD5332 bảng dữ liệu(PDF) 6 Page - Analog Devices |
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AD5332 bảng dữ liệu(HTML) 6 Page - Analog Devices |
6 / 20 page REV. 0 AD5330/AD5331/AD5340/AD5341 –6– AD5331 FUNCTIONAL BLOCK DIAGRAM BUFFER 10-BIT DAC DAC REGISTER INPUT REGISTER INTER- FACE LOGIC POWER-DOWN LOGIC BUF DB9 DB0 .. CS WR CLR LDAC VREF VDD VOUT PD GND AD5331 RESET POWER-ON RESET AD5331 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1DB8 Parallel Data Input. 2DB9 Most Significant Bit of Parallel Data Input. 3VREF Unbuffered Reference Input. 4VOUT Output of DAC. Buffered output with rail-to-rail operation. 5 GND Ground reference point for all circuitry on the part. 6 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. 7 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. 8 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0–VREF or 0–2 VREF. 9 CLR Active low control input that clears all input registers and DAC registers to zero. 10 LDAC Active low control input that updates the DAC registers with the contents of the input registers. 11 PD Power-Down Pin. This active low control pin puts the DAC into power-down mode. 12 VDD Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. 13–20 DB0–DB7 Eight Parallel Data Inputs. AD5331 PIN CONFIGURATION TOP VIEW (Not to Scale) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 AD5331 LDAC GAIN WR CS GND DB8 VREF VOUT PD VDD DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 10-BIT CLR DB9 |
Số phần tương tự - AD5332 |
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Mô tả tương tự - AD5332 |
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