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AD53033 bảng dữ liệu(PDF) 3 Page - Analog Devices |
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AD53033 bảng dữ liệu(HTML) 3 Page - Analog Devices |
3 / 6 page –3– REV. 0 AD53033 Parameter Min Typ Max Units Test Conditions Delay Change vs. Pulsewidth <50 ps VL = 0 V, VH = 2 V Minimum Pulsewidth 3 V Swing 2 ns VL = 0 V, VH = 3 V, 90% Reached, Measure @ 50% 5 V Swing 3 ns VL = 0 V, VH = 5 V, 90% Reached, Measure @ 50% Toggle Rate 250 MHz VL = 0 V, VH = 5 V, VDUT > 3.0 V p-p DYNAMIC PERFORMANCE, INHIBIT Delay Time, Active to Inhibit 1.5 4.0 ns Measured at 50%, VH = +2 V, VL = –2 V Delay Time, Inhibit to Active 1.5 3.5 ns Measured at 50%, VH = +2 V, VL = –2 V Delay Time Matching (Z) ±2.2 ns Z = Delay Time Active to Inhibit Test (Above)— Delay Time Inhibit to Active Test (Above) (Of Worst Two Edges) I/O Spike <200 mV, p-p VH = 0 V, VL = 0 V Rise, Fall Time, Active to Inhibit 3.5 ns VH = +2 V, VL = –2 V (Measured 20%/80% of 1 V Output) Rise, Fall Time, Inhibit to Active 2.2 ns VH = +2 V, VL = –2 V (Measured 20%/80% of 1 V Output) DYNAMIC PERFORMANCE , VTERM Delay Time, VH to VTERM 3.0 ns Measured at 50%, VL = VH = +0.4 V, VTERM = –0.4 V Delay Time, VL to VTERM 5.0 ns Measured at 50%, VL = VH = +0.4 V, VTERM = –0.4 V Delay Time, VTERM to VH and VTERM to VL 4.0 ns Measured at 50%, VL = VH = +0.4 V, VTERM = –0.4 V Overshoot and Preshoot –3.0 + 75 +3.0 + 75 % of Step + mV VH/VL, VTERM = (+0.4 V, –0.4 V), (0.0 V, –2.0 V), (0.0 V, +7.0 V) VTERM Mode Rise Time 4.0 ns VL, VH = 0 V, VTERM = –2 V, 20%–80% VTERM Mode Fall Time 5.5 ns VL, VH = 0 V, VTERM = –2 V, 20%–80% PSRR, DRIVE or TERM Mode 35 dB VS = VS ± 3% Specifications subject to change without notice. COMPARATOR SPECIFICATIONS (All specifications are at TJ = +85 C 5 C, +VS = +12 V 3%, –VS = –7 V = 3% unless otherwise noted. All temperature coefficients are measured at TJ = +75 C to +95 C). Parameter Min Typ Max Units Test Conditions DC INPUT CHARACTERISTICS Offset Voltage (VOS) –25 25 mV CMV = 0 V Offset Voltage (Drift) 50 µV/°C CMV = 0 V HCOMP, LCOMP Bias Current –50 50 µAV IN = 0 V Voltage Range (VCM) –3 8.0 V Differential Voltage (VDIFF) 9.0 V Gain and Linearity –0.05 0.05 % FSR VIN = –3 V to +8 V LATCH ENABLE INPUTS Logic “1” Current (IIH) 250 µA LE, LE = –0.8 V Logic “0” Current (IIL) –250 µA LE, LE = –1.8 V DIGITAL OUTPUTS Logic “1” Voltage (VOH) –0.98 V Q or Q, 50 Ω to –2 V Logic “0” Voltage (VOL) –1.5 V Q or Q, 50 Ω to –2 V Slew Rate 1 V/ns SWITCHING PERFORMANCE Propagation Delay Input to Output 0.9 2.5 ns VIN = 2 V p-p, Latch Enable to Output 2 ns HCOMP = +1 V, LCOMP = +1 V Propagation Delay Temperature Coefficient 2 ps/ °C Propagation Delay Change with Respect to Slew Rate: 0.5 V, 1.0 V, 3.0 V/ns < ±100 ps VIN = 0 V to 5 V Slew Rate: 5.0 V/ns < ±350 ps VIN = 0 V to 5 V Amplitude: 1.0 V, 3.0 V, 5.0 V < ±200 ps VIN = 1.0 V/ns Equivalent Input Rise Time 450 ps VIN = 0 V to 3 V, 3 V/ns Pulsewidth Linearity < ±200 ps VIN = 0 V to 3 V, 3 V/ns, PW = 3 ns–8 ns Settling Time <25 ns Settling to ±8 mV, V IN = 1 V to 0 V Latch Timing Input Pulsewidth <1.5 ns Setup Time <1.0 ns Hold Time <1.0 ns Specifications subject to change without notice. |
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