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AD5260 bảng dữ liệu(PDF) 9 Page - Analog Devices

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AD5260 bảng dữ liệu(HTML) 9 Page - Analog Devices

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REV. 0
AD5232
–9–
Table III. Instruction/Operation Truth Table
Instruction Byte 1
Data Byte 0
Inst
B15
B8
B7
B0
No.
C3 C2 C1 C0 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
Operation
0
0000
XXXX
XX
X
X
XXX
X
No Operation (NOP). Do nothing.
1
0001000A0
X
X
X
X
XXX
X
Write contents of EEMEM(A0) to
RDAC(A0) Register. This command
leaves device in the Read Program power
state. To return part to the idle state,
perform NOP instruction #0.
2
0010000A0
X
X
X
X
XXX
X
SAVE WIPER SETTING. Write con-
tents of RDAC(ADDR) to EEMEM(A0)
3
0011
<< ADDR >>
D7 D6 D5 D4 D3 D2 D1 D0
Write contents of Serial Register Data
Byte 0 to EEMEM(ADDR).
4
0100000A0
XXXXXXXX
Decrement 6 dB right shift contents of
RDAC(A0), stops at all “Zeros.”
5
0101
XXXX
XXXXXXXX
Decrement All 6 dB right shift contents
of all RDAC Registers, stops at all “Zeros.”
6
0110000A0
XXXXXXXX
Decrement contents of RDAC(A0) by
“One,” stops at all “Zeros.”
7
0111
XXXX
XXXXXXXX
Decrement contents of all RDAC Regis-
ters by “One,” stops at all “Zeros.”
8
10000000
XXXXXXXX
RESET. Load all RDACs with their cor-
responding EEMEM previously-saved
values.
9
1001
<< ADDR >>
XXXXXXXX
Write contents of EEMEM(ADDR) to
Serial Register Data Byte 0.
10
1010000A0
XXXXXXXX
Write contents of RDAC(A0) to Serial
Register Data Byte 0.
11
1011000A0
D7 D6 D5 D4 D3 D2 D1 D0
Write contents of Serial Register Data
Byte 0 to RDAC(A0).
12
1100000A0
XXXXXXXX
Increment 6 dB left shift contents of
RDAC(A0), stops at all “Ones.”
13
1101
XXXX
XXXXXXXX
Increment all 6 dB left shift contents
of all RDAC Registers, stops at all “Ones.”
14
1110000A0
XXXXXXXX
Increment contents of RDAC(A0) by
“One,” stops at all “Ones.”
15
1111
XXXX
XXXXXXXX
Increment contents of all RDAC Regis-
ters “One,” stops at all “Ones.”
NOTES
1. The SDO output shifts out the last eight bits of data clocked into the serial register for daisy-chain operation. Exception: following Instruction #9 or #10 the selected internal
register data will be present in data byte 0. Instructions following #9 and #10 must be a full 16-bit data word to completely clock out the contents of the serial register.
2. The RDAC register is a volatile scratch pad register that is refreshed at power-on from the corresponding nonvolatile EEMEM register.
3. The increment, decrement, and shift commands ignore the contents of the shift register Data Byte 0.
4. Execution of the Operation column noted in the table takes place when the
CS strobe returns to logic high.
5. Execution of a NOP instruction minimizes power dissipation.


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