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AD5200 bảng dữ liệu(PDF) 8 Page - Analog Devices |
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AD5200 bảng dữ liệu(HTML) 8 Page - Analog Devices |
8 / 20 page REV. 0 –8– AD5232 SERIAL DATA INTERFACE The AD5232 contains a 4-wire SPI-compatible digital interface (SDI, SDO, CS, and CLK), and uses a 16-bit serial data word loaded MSB first. The format of the SPI-compatible word is shown in Table II. The chip select (CS) pin needs to be held low until the complete data word is loaded into the SDI pin. When CS returns high, the serial data word is decoded accord- ing to the instructions in Table III. The Command Bits (Cx) control the operation of the digital potentiometer. The Address Bits (Ax) determine which register is activated. The Data Bits (Dx) are the values that are loaded into the decoded register. Table IV provides an address map of the EEMEM locations. The last instruction executed prior to a period of no program- ming activity should be the No Operation (NOP) instruction. This will place the internal logic circuitry in a minimum power dissipation state. VALID COMMAND COUNTER COMMAND PROCESSOR AND ADDRESS DECODE SERIAL REGISTER CLK SDI 5V RPULLUP SDO GND PR WP CS AD5232 Figure 3. Equivalent Digital Input-Output Logic The equivalent serial data input and output logic is shown in Figure 3. The open-drain output SDO is disabled whenever chip select CS is logic high. The SPI interface can be used in two slave modes CPHA = 1, CPOL = 1 and CPHA = 0, CPOL = 0. CPHA and CPOL refer to the control bits, which dictate SPI timing in these MicroConverters ® and microprocessors: ADuC812/ADuC824, M68HC11, and MC68HC16R1/916R1. ESD protection of the digital inputs is shown in Figures 4a and 4b. LOGIC PINS VDD GND INPUTS 300 AD5232 Figure 4a. Equivalent ESD Digital Input Protection VDD GND INPUT 300 WP AD5232 Figure 4b. Equivalent WP Input Protection DAISY CHAINING OPERATION The serial data output pin (SDO) serves two purposes. It can be used to read out the contents of the wiper setting and EEMEM values using instruction 10 and 9 respectively. The remaining instructions (#0–8, #11–15) are valid for daisy- chaining multiple devices in simultaneous operations. Daisy-chaining minimizes the number of port pins required from the controlling IC (see Figure 5). The SDO pin contains an open drain N-Channel FET that requires a pull-up resistor if this function is used. As shown in Figure 5, users need to tie the SDO pin of one package to the SDI pin of the next package. Users may need to increase the clock period because the pull-up resistor and the capacitive loading at the SDO-SDI interface may require additional time delay between subsequent packages. If two AD5232’s are daisy-chained, 32 bits of data are required. The first 16 bits go to U2 and the second 16 bits with the same format go to U1. The 16 bits are formatted to contain the 4-bit instruction, followed by the 4-bit address, then the 8 bits of data. The CS should be kept low until all 32 bits are locked into their respective serial registers. The CS is then pulled high to complete the operation. SDI SDO CLK +V RP 2k C SDI SDO CLK CS CS U1 U2 AD5232 AD5232 Figure 5. Daisy-Chain Configuration Using SDO MicroConverter is a registered trademark of Analog Devices, Inc. Table II. 16-Bit Serial Data Word MSB B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 LSB AD5232 C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Command bits are identified as Cx, address bits are Ax, and data bits are Dx. Command instruction codes are defined in Table III. |
Số phần tương tự - AD5200 |
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Mô tả tương tự - AD5200 |
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