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AD28msp01KST bảng dữ liệu(PDF) 10 Page - Analog Devices |
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AD28msp01KST bảng dữ liệu(HTML) 10 Page - Analog Devices |
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10 / 28 page  AD28msp01 REV. A –10– Data Register 1 address = 0x07 Interpolation Filter Input Register (write-only): The 16-bit twos complement values written to this register are input to the resampling interpolation filter. Data Register 2 address = 0x08 ADC Output Register (read-only): The 16-bit twos complement values read from this register are the output of the AD28msp01’s analog-to-digital converter. Data Register 3 address = 0x09 Interpolation Filter Output Register (read-only): The 16-bit twos complement values read from this register are the output of the resampling interpolation filter. Addresses 0x0A—0x1F are reserved. Table II contains the register addresses. Table II. Register Addresses Address Bits 4–0 Register Description 00000 Control Register 0 Data rate and synchronization rate selects, interpolation filter enable 00001 Control Register 1 Filter bypass, test, power-down mode bits, V.32ter mode select bits 00010 Control Register 2 ADC bit and baud rate selects 00011 Control Register 3 DAC bit and baud rate selects 00100 Control Register 4 Receive phase adjust 00101 Control Register 5 Transmit phase adjust 00110 Data Register 0 DAC input register 00111 Data Register 1 Interpolation filter input register 01000 Data Register 2 ADC output register 01001 Data Register 3 Interpolation filter output register 01010 Reserved . . . . . . . . . . . . . . . . . . . . . . . . 11111 Reserved Transferring Data and Control Words to the AD28msp01 Data and control word transfers to the AD28msp01 can only be initiated by the host processor. When transferring data to the AD28msp01, the host processor specifies the destination regis- ter by first transmitting a 16-bit address word (Figure 6) and then transmitting the 16-bit data word. The read/write bit in the address word must be deasserted. The serial data stream from the host processor will consist of a sequence of alternating ad- dress and data words. The AD28msp01 will not write the target register until both the address word and data word are com- pletely transferred. 0 0000 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 READ/WRITE 1 = read 0 = write Address bits [4...0] See Table I. Figure 6. Address Word Example Transferring the following 16-bit words to the AD28msp01 will initialize Control Registers 0–3. Word Transferred Description 0x0000 Control Register 0 Address Word 0x0254 Write this value to Control Register 0 0x0002 Control Register 2 Address Word 0x0031 Write this value to Control Register 2 0x0003 Control Register 3 Address Word 0x0032 Write this value to Control Register 3 0x0001 Control Register 1 Address Word 0x0018 Write this value to Control Register 1 Note that in this example the power-down bits in Control Regis- ter 1 are released (set to 1) only after the AD28msp01 is fully configured by writing to Control Registers 0, 2, and 3. Transferring Data from the AD28msp01 to the Host Data transfers to the host processor can only be initiated by the AD28msp01. When transferring data the AD28msp01 first specifies the source register by transferring a 16-bit address word and then transfers the contents of the source register. Bits 5–14 of the address word will always be forced to zero. When transferring data, the serial data stream from the AD28msp01 will consist of a sequence of alternating address and data words. Transferring Control Words from the AD28msp01 to the Host All control registers in the AD28msp01 are host-readable. To read a control register, the host must transmit a 16-bit address word with the Read/ Write bit set, then transmit a dummy data word. The AD28msp01 will respond by first completing any AD28msp01-to-Host transfer in progress. As soon as the dummy data word is received, the device will transfer a 16-bit word with the control register address and then transmit the contents of the control register. Example The following data streams show how a host can read the con- tents of an AD28msp01 control register: Host AD28msp01 Transfer Transfer Description 0x8001 Read Control Register 1 0x1234 Dummy data word 0x AD28msp01 completes data 0x Transfer in progress 0x0001 Address word 0x0023 Contents of Control Register 1 Serial Port Timing All serial transfers are synchronous. The receive data (SDI) and receive frame sync (SDIFS) are clocked into the device on the falling edge of SCLK. The receive frame sync (SDIFS) must be asserted one SCLK cycle before the first data bit is transferred. When receiving data, the AD28msp01 ignores the receive frame sync pin until the least significant bit is being received. When transmitting data, the AD28msp01 asserts transmit frame sync (SDOFS) and transmit data (SDO) synchronous with the rising edge of SCLK. Transmit frame sync is transmitted one SCLK cycle before the first data bit is transferred. Operating Modes The AD28msp01 is capable of operating in several different modes, as described below. |
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