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AD28MSP01 bảng dữ liệu(PDF) 4 Page - Analog Devices |
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AD28MSP01 bảng dữ liệu(HTML) 4 Page - Analog Devices |
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4 / 28 page  AD28msp01 REV. A –4– The output of the ADC is transferred to the AD28msp01’s se- rial port (SPORT) for transmission to the host DSP processor. D/A CONVERSION The D/A conversion circuitry of the AD28msp01 consists of a sigma-delta digital-to-analog converter (DAC) and a differential output amplifier. DAC The DAC consists of an anti-imaging low-pass filter, an interpo- lation filter, a digital sigma-delta modulator, and an analog smoothing filter. These filters have the same characteristics as the ADC’s anti-aliasing filter and decimation filter. The DAC receives 16-bit samples from the host DSP processor via AD28msp01’s SPORT. If the host processor fails to write a new value to the serial port, the existing (previous) data is read again. The data stream is filtered first by the DAC’s anti- imaging low-pass filter and then by the interpolation filter. The output of the interpolation filter is fed to the DAC’s digital sigma-delta modulator, which converts the 16-bit data to 1-bit samples. The output of the sigma-delta modulator is fed to the AD28msp01’s analog smoothing filter where it is converted into a low-pass filtered, analog voltage. Anti-lmaging Low-Pass Filter The anti-imaging low-pass filter filters the 7.2 kHz, 8.0 kHz, or 9.6 kHz data stream form the SPORTs, and raises the sampling rate to 28.8 kHz, 32.0 kHz, or 38.4 kHz. The anti-imaging low-pass filter can be bypassed by setting the appropriate bit in Control Register 1. This results in a gain change. If the filter is bypassed, the signal must be scaled by the following multipliers to achieve normal levels: 2.046 for 9.6 kHz, 0.987 for 8.0 kHz, and 0.647 for 7.2 kHz. When the filter is bypassed, the host DSP must be able to trans- mit data at the 28.8/32.0/38.4 kHz rates. In this case, re- sampling interpolation should be disabled because of insufficient bandwidth to transmit both ADC and resampled data to the SPORT. Interpolation Filter The interpolation filter contains is a sinc 4 digital filter which raises the sampling rate to 1.7280 MHz by interpolating be- tween the samples. These 16-bit samples are then processed by the digital sigma-delta modulator which noise-shapes the data stream and reduces the sample width to a single bit stream. Analog Smoothing Filter The AD28msp01’s analog smoothing filter consists of a 2nd- order Sallen-Key continuous-time filter and a 3rd-order switched capacitor filter. The Sallen-Key filter has a 3 dB point at approximately 80 kHz. The analog smoothing filter converts the 1.7280 MHz bit stream output of the sigma-delta modulator into a low-pass filtered, differential analog signal. Differential Output Amplifier The differential output amplifier produces the AD28msp01’s analog output (VOUTP, VOUTN). It can drive loads of 2 k Ω or greater and has a maximum differential output voltage swing of 6.312 V peak-to-peak. The output signal is dc biased to the AD28msp01’s on-chip voltage reference (2.5 V nominal) and can be ac coupled directly to a load or dc coupled to an external amplifier. Refer to “Analog Output” in the “Design Consider- ations” section of this data sheet for more information. The VOUTP and VOUTN outputs must be used as differential out- puts; do not use either as a single-ended output. SERIAL PORT The AD28msp01 includes a full-duplex synchronous serial port (SPORT) used to communicate with a host processor. The SPORT is used to read and write all data and control registers in the AD28msp01. The SPORT transfers 16-bit words, MSB first, at a serial clock rate of 1.7280 MHz. When the AD28msp01 exits reset, both the analog circuitry and the digital circuitry are powered down. The serial port will not transmit data to the host until the host sets the digital power- down bit (PWDD) to 1 in Control Register 1. All control regis- ters should be initialized before this bit is set. The SPORT is configured for an externally generated receive frame sync (SDIFS), an internally generated serial clock (SCLK), and an internally generated transmit frame sync (SDOFS). The host processor should be configured for an ex- ternal serial clock and receive frame sync and an internal trans- mit frame sync. DSP Processor Interface The AD28msp01-to-host processor interface is shown in Figure 2. SDO SDOFS SCLK CS SDI SDIFS SERIAL DATA RECEIVE RECEIVE FRAME SYNC SERIAL CLOCK FLAG SERIAL DATA TRANSMIT TRANSMIT FRAME SYNC DSP PROCESSOR AD28msp01 Figure 2. AD28msp01-to-DSP Processor Interface The AD28msp01’s chip select (CS) must be held high to enable SPORT operation. CS can be used to 3-state the SPORT pins and disable communication with the host processor. To use the ADSP-2101 or ADSP-2111 as host DSP processor for the AD28msp01, refer to Figure 3. Note that the ADSP-2101’s SPORT0 communicates with the AD28msp01’s SPORT while the ADSP-2101’s Flag Output (FO) is used to signal the AD28msp01’s CS input. SPORT1 on the ADSP-2101 must be configured for flags and interrupts in this system. SDO SDOFS SCLK CS SDI SDIFS DR0 RFS0 SCLK0 FO DT0 TFS0 ADSP-2101 AD28msp01 Figure 3. AD28msp01-to-ADSP-2101 Interface Figure 4 shows an ADSP-2101 assembly language program that initializes the AD28msp01 and implements a digital loopback through the processor. |
Số phần tương tự - AD28MSP01 |
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Mô tả tương tự - AD28MSP01 |
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