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AD1890 bảng dữ liệu(PDF) 6 Page - Analog Devices

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Giải thích chi tiết về linh kiện  SamplePort Stereo Asynchronous Sample Rate Converters
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AD1890/AD1891
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Output Control Signals
Pin Name
Number
I/O
Description
BKPOL_O
19
I
Bit clock polarity. LO: Normal mode. Output data is valid on rising edges of BCLK_O, changed
on falling. HI: Inverted mode. Output data is valid on falling edges of BCLK_O, changed on rising.
TRGLR_O
18
I
Trigger on LR_O. HI: Changes in LR_O indicate beginning
1 of valid output data. LO: Rising
edge of WCLK_O indicates beginning of valid output data.
MSBDLY_O 17
I
MSB delay. HI: Output data is delayed one BCLK_O after either LR_O (TRGLR_O = HI) or
WCLK_O (TRGLR_O = LO) indicates the beginning of valid output data. Included for I
2S data
format compatibility. LO: No delay.
Miscellaneous
Pin Name
Number
I/O
Description
GPDLYS
1
I
AD1890 ONLY: Group delay—short. HI: Short group delay mode (
≈700 µs). More sensitive to
changes in sample rates (LR clocks). LO: Long group delay mode (
≈3 ms). More tolerant of
sample rate changes. This signal may be asynchronous with respect to MCLK, and dynamically
changed, but is normally pulled up or pulled down on a static basis. AD1891: Short group delay
mode only; this pin is a N/C.
MCLK
2
I
Master clock input. Nominally 16 MHz for sampling frequencies (FS, word rates) from 8 kHz to
56 kHz. Exact frequency is not critical, and does not need to be synchronized to any other clock
or possess low jitter.
RESET
13
I
Active LO reset. Set HI for normal chip operation.
MUTE_O
16
O
Mute output. HI indicates that data is not currently valid due to read and write FIFO memory
pointer overlap. LO indicates normal operation.
MUTE_I
15
I
Mute input. HI mutes the serial output to zeros (midscale). Normally connected to MUTE_O.
Reset LO for normal operation.
SETLSLW
28
I
Settle slowly to changes in sample rates. HI: Slow-settling mode (
≈800 ms). Less sensitive to
sample clock jitter. LO: Fast-settling mode (
≈200 ms). Some narrow-band noise modulation may
result from jitter on LR clocks. This signal may be asynchronous with respect to MCLK, and
dynamically changed, but is normally pulled up or pulled down on a static basis.
N/C
9, 20
No connect. Reserved. Do not connect.
Power Supply Connections
Pin Name
Number
I/O
Description
VDD
7, 22
I
Positive digital voltage supply.
GND
8, 14, 21, 27
I
Digital ground. Pins 14 and 27 need not be decoupled.
NOTE
1The beginning of valid data will be delayed by one BCLK_O if MSBDEL _O is selected (Hl).


Số phần tương tự - AD1890

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Mô tả tương tự - AD1890

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