AD1852

–9–

REV. 0

Table III. SPI Digital Timing

Min

Unit

CCLK HI Pulsewidth

40

ns

CCLK LOW Pulsewidth

40

ns

CDATA Setup Time

10

ns

CDATA Hold Time

10

ns

CLATCH LOW Pulsewidth

10

ns

CLATCH HI Pulsewidth

10

ns

CLATCH Setup Time

4

× t

MCLK

ns

Register Addresses

The lowest two bits of the 16-bit input word are decoded as fol-

lows to set the register that the upper 14 bits will written into.

VOLUME LEFT AND VOLUME RIGHT REGISTERS

A write operation to the left or right volume registers will acti-

vate the “autoramp” clickless volume control feature of the

AD1852. This feature works as follows. The upper 10 bits of the

volume control word will be incremented or decremented by 1 at

a rate equal to the input sample rate. The bottom four bits are

not fed into the autoramp circuit and thus take effect immediately.

This arrangement gives a worst-case ramp time of about 20 ms

for step changes of more than 60 dB, which has been deter-

mined by listening tests to be optimal in terms of preventing the

perception of a “click” sound on large volume changes. See Fig-

ure 8 for a graphical description of how the volume changes

as a function of time.

The 14-bit volume control word is used to multiply the signal,

and therefore the control characteristic is linear, not dB. A constant

dB/step characteristic can be obtained by using a lookup table

word is unsigned (i.e., 0 dB is 11 1111 1111 1111).

Table IV.

Bit 1

Bit 0

Register

0

0

Volume Left

1

0

Volume Right

0

1

Control Register

20ms

TIME

–60

–60

0

0

VOLUME REQUEST REGISTER

ACTUAL VOLUME REGISTER

Figure 8. Smooth Volume Control

SPI Timing

The SPI port is a 3-wire interface with serial data (CDATA),

serial bit clock (CCLK), and data latch (CLATCH). The

data is clocked into an internal shift register on the rising

edge of CCLK. The serial data should change on the falling

edge of CCLK and be stable on the rising edge of CCLK.

The rising edge of CLATCH is used internally to latch the par-

allel data from the serial-to-parallel converter. This rising edge

should be aligned with the falling edge of the last CCLK pulse

in the 16-bit frame. The CCLK can run continuously between

transactions.

Note that the serial control port timing is asynchronous to the

serial data port timing. Changes made to the attenuator level

will be updated on the next edge of the L/

RCLK after the

CLATCH write pulse as shown in Figure 7.

Mute

The AD1852 offers two methods of muting the analog output.

By asserting the MUTE (Pin 23) signal HI, both the left and

right channel are muted. As an alternative, the user can assert

the mute bit in the serial control register (data11) HI. The

AD1852 has been designed to minimize pops and clicks when

muting and unmuting the device by automatically “ramping”

the gain up or down. When the device is unmuted, the volume

returns to the value set in the volume register.