công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
AD1847 bảng dữ liệu(PDF) 6 Page - Analog Devices |
|
AD1847 bảng dữ liệu(HTML) 6 Page - Analog Devices |
6 / 28 page AD1847 REV. B –6– PIN DESCRIPTIONS Parallel Interface Pin Name PLCC TQFP I/O Description SCLK 1 39 I/O Serial Clock. SCLK is a bidirectional signal that supplies the clock as an output to the serial bus when the Bus Master (BM) pin is driven HI and accepts the clock as an input when the BM pin is driven LO. The serial clock output is fixed at 12.288 MHz when XTAL1 is selected, and 11.2896 MHz when XTAL2 is selected. SCLK runs continu- ously. An AD1847 should always be configured as the serial bus master unless it is a slave in a daisy-chained multiple codec system. SDFS 6 44 I/O Serial Data Frame Sync. SDFS is a bidirectional signal that supplies the frame synchroni- zation signal as an output to the serial bus when the Bus Master (BM) pin is driven HI and accepts the frame synchronization signal as an input when the BM pin is driven LO. The SDFS frequency powers up at one half of the AD1847 sample rate (i.e., FRS bit = 0) with two samples per frame and can be programmed to match the sample rate (i.e., FRS bit = 1) with one sample per frame. An AD1847 should always be configured as the serial bus master unless it is a slave in a daisy-chained multiple codec system. SDI 4 42 I Serial Data Input. SDI is used by peripheral devices such as the host CPU or a DSP to supply control and playback data information to the AD1847. All control and playback transfers are 16 bits long, MSB first. SDO 5 43 O Serial Data Output. SDO is used to supply status/index readback and capture data infor- mation to peripheral devices such as the host CPU or a DSP. All status/index readback and capture data transfers are 16 bits long, MSB first. Three-state output driver. RESET 11 5 I Reset. The RESET signal is active LO. The assertion of this signal will initialize the on-chip registers to their default values. See the “Control Register Definitions” section for a description of the contents of the control registers after RESET is deasserted. PWRDOWN 12 6 I Powerdown. The PWRDOWN signal is active LO. The assertion of this signal will reset the on-chip control registers (identically to the RESET signal) and will also place the AD1847 in a low power consumption mode. VREF and all analog circuitry are disabled. BM 33 27 I Bus Master. The assertion (HI) of this signal indicates that the AD1847 is the serial bus master. The AD1847 will then supply the serial clock (SCLK) and the frame sync (SDFS) signals for the serial bus. One and only one AD1847 should always be configured as the serial bus master. If BM is connected to logic LO, the AD1847 is configured as a bus slave, and will accept the SCLK and SDFS signals as inputs. An AD1847 should only be configured as a serial bus slave when an AD1847 serial bus master already exists, in daisy-chained multiple codec systems. TSO 7 1 O Time Slot Output. This signal is asserted HI by the AD1847 coincidentally with the LSB of the last time slot used by the AD1847. Used in daisy-chained multiple codec systems. TSI 8 2 I Time Slot Input. The assertion of this signal indicates that the AD1847 should immedi- ately use the next three time slots (TSSEL = 1) or the next six time slots (TSSEL = 0) and then activate the TSO pin to enable the next device down the TDM chain. TSI should be driven LO when the AD1847 is the bus master or in single codec systems. Used in daisy-chained multiple codec systems. CLKOUT 44 38 O Clock Output. This signal is the buffered version of the crystal clock output and the fre- quency is dependent on which crystal is selected. This pin can be three-stated by driving the BM pin LO or by programming the CLKTS bit in the Pin Control Register. See the “Control Registers” section for more details. The CLKOUT frequency is 12.288 MHz when XTAL1 is selected and 16.9344 MHz when XTAL2 is selected. Analog Signals Pin Name PLCC TQFP I/O Description L_LINE1 23 17 I Left Line Input #1. Line level input for the #1 left channel. R_LINE1 17 11 I Right Line Input #1. Line level input for the #1 right channel. L_LINE2 22 16 I Left Line Input #2. Line level input for the #2 left channel. R_LINE2 18 12 I Right Line Input #2. Line level input for the #2 right channel. L_AUX1 26 20 I Left Auxiliary Input #1. Line level input for the AUX1 left channel. R_AUX1 27 21 I Right Auxiliary Input #1. Line level input for the AUX1 right channel. L_AUX2 32 26 I Left Auxiliary Input #2. Line level input for the AUX2 left channel. R_AUX2 31 25 I Right Auxiliary Input #2. Line level input for the AUX2 right channel. L_OUT 30 24 O Left Line Output. Line level output for the left channel. R_OUT 28 22 O Right Line Output. Line level output for the right channel. |
Số phần tương tự - AD1847 |
|
Mô tả tương tự - AD1847 |
|
|
Link URL |
Chính sách bảo mật |
ALLDATASHEET.VN |
Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |