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AD1846 bảng dữ liệu(PDF) 7 Page - Analog Devices

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AD1846
REV. A
–7–
PIN DESCRIPTION
Parallel Interface
Pin Name
PLCC
I/O
Description
CDRQ
12
O
Capture Data Request. The assertion of this signal indicates that the Codec has a captured
audio sample from the ADC ready for transfer. This signal will remain asserted until all the
bytes from the capture buffer have been transferred.
CDAK
11
I
Capture Data Acknowledge. The assertion of this active LO signal indicates that the RD
cycle occurring is a DMA read from the capture buffer.
PDRQ
14
O
Playback Data Request. The assertion of this signal indicates that the Codec is ready for
more DAC playback data. The signal will remain asserted until all the bytes needed for a
playback sample have been transferred.
PDAK
13
I
Playback Data Acknowledge. The assertion of this active LO signal indicates that the WR
cycle occurring is a DMA write to the playback buffer.
ADR1:0
9 & 10
I
Codec Addresses. These address pins are asserted by the Codec interface logic during a con-
trol register/PIO access. The state of these address lines determine which register is accessed.
RD
60
I
Read Command Strobe. This active LO signal defines a read cycle from the Codec. The
cycle may be a read from the control/PIO registers, or the cycles could be a read from the
Codec’s DMA sample registers.
WR
61
I
Write Command Strobe. This active LO signal indicates a write cycle to the Codec. The
cycle may be a write to the control/PIO registers, or the cycle could be a write to the Codec’s
DMA sample registers.
CS
59
I
AD1846 Chip Select. The Codec will not respond to any control/PIO cycle accesses unless
this active LO signal is LO. This signal is ignored during DMA transfers.
DATA7:0
3–6 &
I/O
Data Bus. These pins transfer data and control information between the Codec and the host.
65–68
DBEN
63
O
Data Bus Enable. This pin enables the external bus drivers. This signal is normally HI.
For control register/PIO cycles,
DBEN
= (WR OR RD) AND CS
For DMA cycles,
DBEN
= (WR OR RD) AND (PDAK OR CDAK)
DBDIR
62
O
Data Bus Direction. This pin controls the direction of the data bus transceiver. HI enables
writes from the host to the AD1846; LO enables reads from the AD1846 to the host bus.
This signal is normally HI.
For control register/PIO cycles,
DBDIR = RD AND CS
For DMA cycles,
DBDIR = RD AND (PDAK OR CDAK)


Số phần tương tự - AD1846

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Analog Devices
AD1846 AD-AD1846_15 Datasheet
249Kb / 28P
   Low Cost Parallel-Port 16-Bit SoundPort Stereo Codec
REV. A
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Mô tả tương tự - AD1846

nhà sản xuấttên linh kiệnbảng dữ liệuGiải thích chi tiết về linh kiện
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Analog Devices
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REV. A
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