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AD1317KZ bảng dữ liệu(PDF) 9 Page - Analog Devices |
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AD1317KZ bảng dữ liệu(HTML) 9 Page - Analog Devices |
9 / 12 page AD1317 –9– REV. A FUNCTIONAL DESCRIPTION The AD1317 is an ultrahigh speed window comparator designed for use in general purpose instrumentation and automatic test equipment. The internal connections for windowing operation keep the capacitance at the critical common input (VINA/B) well below what could normally be obtained using separate input pins. Another key feature is that the front end circuitry may be dis- abled, decreasing input bias currents to 50 pA (typical). This enables sensitive dc current testing without having to physically disconnect the AD1317’s input from the circuit. The comparator’s outputs would normally be latched to maintain absolute logic levels prior to inhibiting the input. High speed comparators using bipolar process technology usu- ally have input bias currents in the 1 µA to 20 µA range, and the AD1317 is no exception in this regard. This occurs because the input devices usually have low current gain but must be oper- ated at high currents to obtain the widest possible bandwidth. Careful design minimizes variations in the AD1317’s bias cur- rent with respect to both differential and common-mode input variations. This translates directly to a high equivalent input resistance, the minimum of which occurs with zero differential input. The typical input resistance of the AD1317’s common input under this condition is on the order of 4 megohms. Many ATE applications have required input dividers/buffers to reduce standard logic voltages to levels which can be processed by “687” type comparators. These dividers have also reduced the slew rates at which the comparators must properly function. The AD1317’s 9 volt differential and common-mode input ranges and 2.5 V/ns slew rate capability make these buffer cir- cuits unnecessary in most applications. Separate, complementary latch inputs are provided for each comparator. These may be driven by differential or single-ended sources ranging from ECL to HCMOS logic. When using the comparator’s transparent mode, the latch inputs may be tied anywhere within their common-mode range with a maximum differential of 4 V. Symmetrical hysteresis may also be generated by applying a small differential voltage to the latch inputs (see HYSTERESIS). The AD1317’s outputs are standard emitter followers with ECL- compatible voltage swings. The recommended output termina- tion is 50 Ω to –2 V. Larger value termination resistors connected to –VS may be used, but will reduce edge fidelity. Typical output rise and fall times (20%–80%) are 1 ns with a 50 Ω, 10 pF load. The maximum output source current is 40 mA. THERMAL CONSIDERATIONS The AD1317 is provided in a 0.450" × 0.450", 16-lead (bottom brazed) gull wing, surface mount package with a typical θ JC (junction-to-case thermal resistance) of 17.5 °C/W. Thermal resistance θ CA (case to ambient) vs. air flow for the AD1317 in this package is shown in Figure 25. The improvement in thermal resistance vs. air flow begins to flatten out just above 400 lfm 1, 2. NOTES 1lfm is airflow in linear feet/minute. 2For convection cooled systems, the minimum recommended airflow is 400 lfm. Figure 25. Case-to-Ambient Thermal Resistance vs. Air Flow DISPERSION Propagation delay dispersion is the change in device propagation delay which results from changes in the input signal conditions. Dispersion is an indicator of how well the comparator’s frontend design balances the conflicting requirements of high gain and wide bandwidth. High gain is needed to ensure that small over- drives will produce valid logic outputs without an increase in propagation delay, while wide bandwidth enables the compara- tor to handle fast input slew rates. The input signal criteria used to determine the AD1317’s dispersion performance are ampli- tude, overdrive and slew rate for both standard CMOS and ECL signal levels. HYSTERESIS The customary technique for introducing hysteresis into a com- parator uses positive feedback as shown in Figure 27. The major problems with this approach are that the amount of hysteresis varies with the output logic levels and that the hysteresis is not symmetrical around zero. The AD1317 does not use this technique. Instead, hysteresis is generated by introducing a differential voltage between LE and LE as shown in Figure 28. Hysteresis generated in this manner is independent of output swing and is symmetrical around zero. The variation of hysteresis with input voltage is shown in Figure 29; the useful hysteresis range is about 20 mV. LAYOUT CONSIDERATIONS Like any high speed device, the AD1317 requires careful layout and bypassing to obtain optimum performance. Oscillations are generally caused by coupling from an output to the high imped- ance inputs. All drive impedances should be as low as possible, and lead lengths should be minimized. A ground plane should be used to provide low impedance return paths. Care should be taken in selecting sockets for incoming or other testing to mini- mize lead inductance, and sockets are not recommended for production use. |
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Mô tả tương tự - AD1317KZ |
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