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ADS8608A8A-75 bảng dữ liệu(PDF) 2 Page - A-Data Technology |
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2 / 8 page A-Data ADS8608A8A Pin Description PIN NAME FUNCTION CLK System Clock Active on the positive edge to sample all inputs. CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least on cycle prior new command. Disable input buffers for power down in standby /CS Chip Select Disables or Enables device operation by masking or enabling all input except CLK, CKE and L(U)DQM A0~A12 Address Row / Column address are multiplexed on the same pins. Row address : A0~A12 Column address : A0~A9 BS0~BS1 Banks Select Selects bank to be activated during row address latch time. Selects bank for read / write during column address latch time. DQ0~DQ7 Data Data inputs / outputs are multiplexed on the same pins. /RAS Row Address Strobe Latches row addresses on the positive edge of the CLK with /RAS low /CAS Column Address Strobe Latches Column addresses on the positive edge of the CLK with /CAS low /WE Write Enable Enables write operation and row recharge. VCC/VSS Power Supply/Ground Power and Ground for the input buffers and the core logic. VCCQ/VSSQ Data Output Power/Ground Power supply for output buffers. NC No Connection This pin is recommended to be left No Connection on the device. Block Diagram CLK CKE Clock Generator Address /CS /RAS /CAS /WE DQM Mode Register Address Buffer & Refresh Counter Column Address Buffer & Refresh Counter Bank0 Bank2 Bank3 Bank1 Amplifier Column Decoder Data Control Circuit DQ Rev 1.0 December, 2001 2 |
Số phần tương tự - ADS8608A8A-75 |
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Mô tả tương tự - ADS8608A8A-75 |
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