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STK672-401C-E bảng dữ liệu(PDF) 10 Page - Sanyo Semicon Device |
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STK672-401C-E bảng dữ liệu(HTML) 10 Page - Sanyo Semicon Device |
10 / 19 page STK672-401C-E No.A2137-10/19 [MODE1, MODE2, and MODE3 (Excitation mode and timing mode selection)] (1) Pin circuit type: TTL level Schmitt trigger input (2) Excitation mode selection (See the application circuit example page for details on excitation mode selection.) (3) Valid mode setting timing: Do not change the mode within the ±7 μs period around any rising or falling edge on the CLK input signal. Mode Setting Acquisition Timing [RESET (Whole system reset)] (1) Pin circuit type: TTL level Schmitt trigger input (2) Function: The reset signal to this hybrid IC's internal sequencer can be selected to be either the hybrid IC internal power-on reset function or an external signal. To operate the hybrid IC internal sequencer from the hybrid IC internal power-on reset signal, connect the hybrid IC's pin 14 to VDD. The hybrid IC internal reset signal is generated with a timing such that it is output to internal circuits when VDD is in the range 2.9 to 3.9V. Alternatively, if an external signal is used as the reset signal, it must have the timing relative to the rise of the VDD voltage shown in the figure below. Note that the reset pulse must have a pulse width of at least 10 μs. • External reset and power supply application sequence CLK input System clock Mode setting Mode switching clock IC internal setting state Phase excitation clock Mode switching timing Phase excitation counter up/down 4.5V VDD: 5V power supply (hybrid IC pin 9) RESET: Hybrid IC pin 14 At least 10 μs |
Số phần tương tự - STK672-401C-E |
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Mô tả tương tự - STK672-401C-E |
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