HUFA76407DK8T_10 datasheet(7/12 Pages) FAIRCHILD

tên linh kiện	HUFA76407DK8T

Giải thích chi tiết về linh kiện	3.5A, 60V, 0.105 Ohm, Dual N-Channel, Logic Level UltraFET짰 Power MOSFET

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Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, TJM, and the

thermal resistance of the heat dissipating path determines

the maximum allowable device power dissipation, PDM, in an

application. Therefore the application’s ambient

temperature, TA (oC), and thermal resistance RθJA (oC/W)

must be reviewed to ensure that TJM is never exceeded.

Equation 1 mathematically represents the relationship and

serves as the basis for establishing the rating of the part.

In using surface mount devices such as the SOP-8 package,

the environment in which it is applied will have a significant

influence on the part’s current and maximum power

dissipation ratings. Precise determination of PDM is complex

and influenced by many factors:

1. Mounting pad area onto which the device is attached and

whether there is copper on one side or both sides of the

board.

2. The number of copper layers and the thickness of the

board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For non steady state applications, the pulse width, the

duty cycle and the transient thermal response of the part,

the board and the environment they are in.

Fairchild provides thermal information to assist the

designer’s preliminary application evaluation. Figure 23

defines the RθJA for the device as a function of the top

copper (component side) area. This is for a horizontally

positioned FR-4 board with 1oz copper after 1000 seconds

of steady state power with no air flow. This graph provides

the necessary information for calculation of the steady state

junction temperature or power dissipation. Pulse applications

can be evaluated using the Fairchild device Spice thermal

model or manually utilizing the normalized maximum

transient thermal impedance curve.

Displayed on the curve are RθJA values listed in the

Electrical Specifications table. The points were chosen to

depict the compromise between the copper board area, the

thermal resistance and ultimately the power dissipation,

PDM.

Thermal resistances corresponding to other copper areas

can be obtained from Figure 23 or by calculation using

Equation 2. RθJA is defined as the natural log of the area

times a cofficient added to a constant. The area, in square

inches is the top copper area including the gate and source

pads.

While Equation 2 describes the thermal resistance of a

single die, several of the new UltraFETs are offered with two

die in the SOP-8 package. The dual die SOP-8 package

introduces an additional thermal component, thermal

coupling resistance, Rθβ. Equation 3 describes Rθβ as a

function of the top copper mounting pad area.

The thermal coupling resistance vs. copper area is also

graphically depicted in Figure 23. It is important to note the

thermal resistance (RθJA) and thermal coupling resistance

(Rθβ) are equivalent for both die. For example at 0.1 square

inches of copper:

RθJA1 = RθJA2 = 159oC/W

Rθβ1 = Rθβ2 = 97oC/W

TJ1 and TJ2 define the junction temerature of the respective

die. Similarly, P1 and P2 define the power dissipated in each

die. The steady state junction temperature can be calculated

using Equation 4 for die 1and Equation 5 for die 2.

Example: To calculate the junction temperature of each die

when die 2 is dissipating 0.5 Watts and die 1 is dissipating 0

Watts. The ambient temperature is 70oC and the package is

mounted to a top copper area of 0.1 square inches per die.

Use Equation 4 to calulate TJ1 and and Equation 5 to

calulate TJ2.

.

TJ1 = (0 Watts)(159oC/W) + (0.5 Watts)(97oC/W) + 70oC

TJ1 = 119oC

(EQ. 1

PDM

TJM TA

–

()

RθJA

-------------------------------

=

(EQ. 2)

RθJA 103.2 24.3

Area

()

ln

×

–

=

0

50

100

150

200

250

300

0.001

0.01

0.1

1

AREA, TOP COPPER AREA (in2) PER DIE

191 oC/W - 0.027in2

228 oC/W - 0.006in2

FIGURE 23. THERMAL RESISTANCE vs MOUNTING PAD AREA

RθJA = 103.2 - 24.3 * ln(AREA)

Rθβ = 46.4 - 21.7 * ln(AREA)

(EQ. 3)

Rθβ

46.4 21.7

Area

()

ln

×

–

=

(EQ. 4)

TJ1 P1RθJA P2Rθβ TA

++

=

HUFA76407DK8T_F085 Rev. C1

www.fairchildsemi.com

7

HUFA76407DK8T_F085

Số phần tương tự - HUFA76407DK8T_10

nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
ON Semiconductor	HUFA76407DK8T-F085	976Kb / 7P	Dual N-Channel Logic Level UltraFET짰 Power MOSFET 60 V, 3.5 A, 105 m廓 September-2017, Rev. 2

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