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STA2500D bảng dữ liệu(PDF) 5 Page - STMicroelectronics |
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STA2500D bảng dữ liệu(HTML) 5 Page - STMicroelectronics |
5 / 58 page STA2500D List of figures Doc ID 16067 Rev 2 5/58 List of figures Figure 1. Block diagram and electrical schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 2. Pinout (bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 3. Active high clock request input and output combined with UART or SPI . . . . . . . . . . . . . . 28 Figure 4. Active low clock request input and output combined with UART . . . . . . . . . . . . . . . . . . . . 28 Figure 5. Active low clock request input and output combined with SPI . . . . . . . . . . . . . . . . . . . . . . 28 Figure 6. Deep sleep mode entry and wake-up through H4 UART . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 7. Entering deep sleep mode through enhanced H4 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 8. Wake-up by the host through enhanced H4 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 9. Wake-up by the Bluetooth controller with data transmission to the host, through enhanced H4 SPI 34 Figure 10. Deep sleep mode entry and wake-up through H4 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 11. Entering deep sleep mode, pending data on UART interface, through UART with handshake 36 Figure 12. Wakeup by host through UART with handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figure 13. PTA diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 14. WLAN master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 15. Bluetooth master. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 16. SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 17. SPI data transfer timing for data length of 8 bits and lsb first, full duplex . . . . . . . . . . . . . . 42 Figure 18. SPI setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 19. PCM (A-law, µ-law) standard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 20. Linear mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 21. Multislot operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 22. PCM interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 23. UART transport layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 24. LFBGA48 (6x6x1.4mm) mechanical data and package dimensions . . . . . . . . . . . . . . . . . 50 Figure 25. Package markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 |
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