ST10F272B_12 datasheet(9/188 Pages) STMICROELECTRONICS

tên linh kiện	ST10F272B

Giải thích chi tiết về linh kiện	16-bit MCU with 256 Kbyte Flash memory and 12/20 Kbyte RAM

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nhà sản xuất	STMICROELECTRONICS [STMicroelectronics]

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9 / 188 page

ST10F272B/ST10F272E

List of figures

Doc ID 11917 Rev 3

9/188

List of figures

Figure 1.

Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 2.

Pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 3.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 4.

ST10F272 on-chip memory mapping (ROMEN=1 / XADRS = 800Bh - Reset value). . . . . 27

Figure 5.

Flash structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 6.

CPU block diagram (MAC Unit not included) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 7.

MAC unit architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 8.

X-Interrupt basic structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 9.

Block diagram of GPT1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 10.

Block diagram of GPT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 11.

Block diagram of PWM module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 12.

Connection to single CAN bus via separate CAN transceivers . . . . . . . . . . . . . . . . . . . . . 80

Figure 13.

Connection to single CAN bus via common CAN transceivers. . . . . . . . . . . . . . . . . . . . . . 80

Figure 14.

Connection to two different CAN buses (e.g. for gateway application). . . . . . . . . . . . . . . . 81

Figure 15.

Connection to one CAN bus with internal Parallel Mode enabled . . . . . . . . . . . . . . . . . . . 81

Figure 16.

Asynchronous power-on RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Figure 17.

Asynchronous power-on RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Figure 18.

Asynchronous hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Figure 19.

Asynchronous hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Figure 20.

Synchronous short / long hardware RESET (EA = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Figure 21.

Synchronous short / long hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Figure 22.

Synchronous long hardware RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Figure 23.

Synchronous long hardware RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Figure 24.

SW / WDT unidirectional RESET (EA = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Figure 25.

SW / WDT unidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Figure 26.

SW / WDT bidirectional RESET (EA=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Figure 27.

SW / WDT bidirectional RESET (EA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Figure 28.

SW / WDT bidirectional RESET (EA=0) followed by a HW RESET . . . . . . . . . . . . . . . . . 102

Figure 29.

Minimum external reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Figure 30.

System reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 31.

Internal (simplified) reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

Figure 32.

Example of software or watchdog bidirectional reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . 105

Figure 33.

Example of software or watchdog bidirectional reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . 106

Figure 34.

PORT0 bits latched into the different registers after reset . . . . . . . . . . . . . . . . . . . . . . . . 109

Figure 35.

External RC circuitry on RPD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Figure 36.

Port2 test mode structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Figure 37.

Supply current versus the operating frequency (RUN and IDLE modes) . . . . . . . . . . . . . 138

Figure 38.

A/D conversion characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

Figure 39.

A/D converter input pins scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

Figure 40.

Charge sharing timing diagram during sampling phase . . . . . . . . . . . . . . . . . . . . . . . . . . 146

Figure 41.

Anti-aliasing filter and conversion rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148

Figure 42.

Input / output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Figure 43.

Float waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151

Figure 44.

Generation mechanisms for the CPU clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152

Figure 45.

ST10F272 PLL jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158

Figure 46.

Crystal oscillator and resonator connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

Figure 47.

32kHz crystal oscillator connection diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Figure 48.

External clock drive XTAL1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162

Số phần tương tự - ST10F272B_12

nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
STMicroelectronics	ST10F272B	1Mb / 181P	16-bit MCU with 256 Kbyte Flash memory and 12/20 Kbyte RAM

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Mô tả tương tự - ST10F272B_12

nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
STMicroelectronics	ST10F272B	1Mb / 181P	16-bit MCU with 256 Kbyte Flash memory and 12/20 Kbyte RAM
	ST10F272Z2	2Mb / 189P	16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
	ST10F272	3Mb / 179P	16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
	ST10F272M	3Mb / 175P	16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
	ST10F272M	1Mb / 176P	16-bit MCU with 256 Kbyte Flash memory and 20 Kbyte RAM
	ST10F271Z1	3Mb / 185P	16-bit MCU with 128 Kbyte Flash memory and 12 Kbyte RAM
	ST10F271	2Mb / 173P	16-bit MCU with 128 Kbyte Flash memory and 12 Kbyte RAM
	ST10F271B	1Mb / 180P	16-bit MCU with 128 Kbyte Flash memory and 8/12 Kbyte RAM
	ST10F273Z4	1Mb / 188P	16-bit MCU with 512 Kbyte Flash memory and 36 Kbyte RAM January 2008 Rev 2
	ST10F273E	1Mb / 179P	16-bit MCU with 512 Kbyte Flash memory and 36 Kbyte RAM

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