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MC14175BDR2G bảng dữ liệu(PDF) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2011
June, 2011 − Rev. 7
1
Publication Order Number:
MC14175B/D
MC14175B
Quad Type D Flip-Flop
The MC14175B quad type D flip−flop is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. Each of the four flip−flops is positive−edge
triggered by a common clock input (C). An active−low reset input (R)
asynchronously resets all flip−flops. Each flip−flop has independent
Data (D) inputs and complementary outputs (Q and Q). These devices
may be used as shift register elements or as type T flip−flops for
counter and toggle applications.
Features
Complementary Outputs
Static Operation
All Inputs and Outputs Buffered
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Output Compatible with Two Low−Power TTL Loads or One
Low−Power Schottky TTL Load
Functional Equivalent to TTL 74175
These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Parameter
Symbol
Value
Unit
DC Supply Voltage Range
VDD
−0.5 to +18.0
V
Input or Output Voltage Range
(DC or Transient)
Vin, Vout
−0.5 to VDD
+ 0.5
V
Input or Output Current (DC or Transient)
per Pin
Iin, Iout
±10
mA
Power Dissipation per Package (Note 1)
PD
500
mW
Ambient Temperature Range
TA
−55 to +125
°C
Storage Temperature Range
−65 to +150
°C
Lead Temperature (8−Second Soldering)
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating: Plastic “P and D/DW”
Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
Device
Package
Shipping
ORDERING INFORMATION
http://onsemi.com
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
MC14175BFELG SOEIAJ−16
(Pb−Free)
2000/Tape & Reel
MC14175BDR2G
SOIC−16
(Pb−Free)
2500/Tape & Reel
MC14175BDG
SOIC−16
(Pb−Free)
48 Units/Rail
MC14175BCPG
PDIP−16
(Pb−Free)
500 Units/Rail
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G
= Pb−Free Package
MARKING
DIAGRAMS
PDIP−16
P SUFFIX
CASE 648
SOIC−16
D SUFFIX
CASE 751B
1
16
14175BG
AWLYWW
SOEIAJ−16
F SUFFIX
CASE 966
1
16
MC14175B
ALYWG
16
1
MC14175BCP
AWLYYWWG
1
1
1


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