MC74LCX74

http://onsemi.com

2

Figure 1. Pinout: 14−Lead (Top View)

13

14

12

11

10

9

8

2

1

34567

CP2 SD2O2

O2

CD1

D1 CP1

SD1O1

O1

GND

Figure 2. Logic Diagram

O1

SD1

Q

4

5

D1

D

2

CP1

CP

3

CD1

1

O1

Q

6

SD

CD

O2

SD2

Q

10

9

D2

D

12

CP2

CP

11

CD2

13

O2

Q

8

SD

CD

PIN NAMES

Pins

Function

CP1, CP2

Clock Pulse Inputs

D1−D2

Data Inputs

CD1, CD2

Direct Clear Inputs

SD1, SD2

Direct Set Inputs

On−On

Outputs

TRUTH TABLE

Inputs

Outputs

SDn

CDn

CPn

Dn

On

On

Operating Mode

L

H

X

X

H

L

Asynchronous Set

H

L

X

X

L

H

Asynchronous Clear

L

L

X

X

H

H

Undetermined

H

H

↑

h

H

L

Load and Read Register

H

H

↑

l

L

H

H

H

↑

X

NC

NC

Hold

H

= High Voltage Level

h

= High Voltage Level One Setup Time Prior to the Low−to−High Clock Transition

L

= Low Voltage Level

l

= Low Voltage Level One Setup Time Prior to the Low−to−High Clock Transition

NC = No Change

X

= High or Low Voltage Level and Transitions are Acceptable

↑

= Low−to−High Transition

↑

= Not a Low−to−High Transition