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CAHCT138QPWRG4Q1 bảng dữ liệu(PDF) 1 Page - Texas Instruments |
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CAHCT138QPWRG4Q1 bảng dữ liệu(HTML) 1 Page - Texas Instruments |
1 / 12 page SN74AHCT138QQ1 3LINE TO 8LINE DECODER/DEMULTIPLEXER SGDS022A − FEBRUARY 2002 − REVISED APRIL 2008 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Qualified for Automotive Applications D EPIC (Enhanced-Performance Implanted CMOS) Process D Inputs Are TTL-Voltage Compatible D Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems D Incorporates Three Enable Inputs to Simplify Cascading and/or Data Reception D Latch-Up Performance Exceeds 250 mA Per JESD 17 D ESD Protection Exceeds 2000 V Per MIL-STD-833, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) description The SN74AHCT138Q 3-line to 8-line decoder/demultiplexer is designed to be used in high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications. ORDERING INFORMATION{ TA PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING −40 °C to 125°C SOIC − D Tape and reel SN74AHCT138QDRQ1 AHCT138Q −40 °C to 125°C TSSOP − PW Tape and reel SN74AHCT138QPWRQ1 HB138Q † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. Copyright 2008, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 A B C G2A G2B G1 Y7 GND VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 D OR PW PACKAGE (TOP VIEW) |
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