SN54ACT8999, SN74ACT8999

SCANPATH SELECTORS WITH 8BIT BIDIRECTIONAL DATA BUSES

SCANCONTROLLED IEEE STD 1149.1 (JTAG) TAP MULTIPLEXERS

SCAS158D − JUNE 1990 − REVISED DECEMBER 1996

3

POST OFFICE BOX 655303

POST OFFICE BOX 1443

functional block description

The ’ACT8999 implements two separate functions in one package. The primary function of the device is to

include a selected secondary scan path in the system’s primary scan path to enable a PBC to perform controlling

and observing test functions on the selected path. This is accomplished by driving the TMS terminal(s) of a

secondary scan path with one of the DTMS pins of the device. This approach allows a system to have built-in

testability at all levels without requiring that the primary-system scan path always include all subsystem scan

paths. As a result, test throughput is improved and the amount of test data that must be interpreted is reduced.

The device includes error-detection circuitry that prevents the user from inadvertently activating more than one

secondary scan path at a time.

Another function of the device is provided by the 8-bit identification bus. This bus can be hardwired with pullup

and pulldown resistors to supply an identification code to the test controller(s) to verify that test operations are

being performed on the proper portion of the system. The bus can also transfer data and instructions to another

device, such as a local or remote bus controller, and pass control of the scan-path select function to that device.

This frees the primary controller to activate another secondary scan path elsewhere in the system or perform

higher-level test control functions. When the RBC is ready to return control of the device, interrupt signals alert

the primary controller.

The least-significant bit (LSB) of any value scanned into any register of the device is the first bit shifted in

(nearest to TDO). The most-significant bit (MSB) is the last bit shifted in (nearest to TDI). The ’ACT8999 is

divided into functional blocks as detailed below.

test ports

The test ports decode the signals on TCK, TMS, OTMS, and TRST to control the operation of the circuit. Each

test port includes a TAP controller that issues the proper control instructions to the data registers according to

the IEEE Standard 1149.1 protocol. The TAP controller state diagram is shown in Figure 1. Two test ports are

included on the ’ACT8999, allowing different test controllers to command different sections of the device.

TMS circuit

The TMS circuit decodes bits in the select and control registers to determine which one, if any, of the DTMS

pins (which provide mode-select signals to the secondary scan path(s)) follow the TMS pin or OTMS pin. The

unselected DTMS pins are set by the circuit to a static high or low level.

instruction register

The instruction register (IR) is an 8-bit-wide serial-shift register that issues commands to the device. Data is

input to the instruction register via TDI or DTDI and shifted out via TDO. All device operations are initiated by

loading the proper instruction or sequence of instructions into the IR.

data registers

Six parallel data registers are included in the ’ACT8999: bypass, control, counter, boundary-scan, ID-bus, and

select. The ID bus register is a part of the boundary-scan register. Each data register is serially loaded via TDI

or DTDI and outputs data via TDO. Table 1 summarizes the registers in the ’ACT8999.

Table 1. Register Summary

REGISTER NAME

LENGTH (BITS)

FUNCTION

Instruction

8

Issue command information to the device

Remote Instruction

8

Issue command information to the select register

Control

13

Configuration and enable control

Counter

8

Count events on DCI, output interrupts via DCO

Select

8

Select one of four DTMS pins to follow TMS or OTMS

Boundary Scan

15

Capture and force test data at device periphery

ID Bus

8

Pass test commands and data between a PBC and RBC(s)

Bypass

1

Remove the ’ACT8999 from the scan path