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ISL267450IUZ bảng dữ liệu(PDF) 8 Page - Intersil Corporation |
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ISL267450IUZ bảng dữ liệu(HTML) 8 Page - Intersil Corporation |
8 / 19 page ISL267450 8 FN8341.0 August 10, 2012 tQUIET Quiet Time Before Sample 25 ns tCSS CS Falling Edge to SCLK Falling Edge Setup Time 10 ns tDISABLE CS Falling Edge to SDATA Disable Time (Note 9) Extrapolated back to true bus relinquish 10 35 µs tSWH SCLK High Pulsewidth 0.4 x tSCLK 0.6 x tSCLK ns tSWL SCLK Low Pulsewidth 0.4 x tSCLK 0.6 x tSCLK ns tCLKDV SCLK Falling Edge to SDATA Valid 40 ns tSDH SCLK Falling Edge to SDATA Hold 10 ns tACQ Acquisition Time (Note 8) ns tCSW CS Pulse Width 10 ns tCDV CS Falling Edge to SDATA Valid 20 ns NOTE: 9. During characterization, tDISABLE is measured from the release point with a 10pF load (see Figure 2 on page 8) and the equivalent timing using the AD7450 loading (50pF) is calculated. Electrical Specifications Limits established by characterization and are not production tested. VDD = +3.0V to +3.3V, FSCLK = 15MHz, FS = 833kSPS, VREF = 1.25V, FIN = 200kHz; VREF = 2.5V; VCM = VREF, TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS FIGURE 1. SERIAL INTERFACE TIMING DIAGRAM FIGURE 2. EQUIVALENT LOAD CIRCUIT OUTPUT PIN CL 10 pF VDD 2.85k RL |
Số phần tương tự - ISL267450IUZ |
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Mô tả tương tự - ISL267450IUZ |
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