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ISL2671286 bảng dữ liệu(PDF) 5 Page - Intersil Corporation |
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ISL2671286 bảng dữ liệu(HTML) 5 Page - Intersil Corporation |
5 / 15 page ISL2671286 5 FN7863.0 November 1, 2011 thDO Output Data Remains Valid After DCLOCK ↓ CLOAD = 100pF 15 30 ns tf DOUT Fall Time See test circuits; Figure 4 1 100 ns tR DOUT Rise Time See test circuits; Figure 4 1 100 ns tCSD Delay Time, CS/SHDN ↓ to DCLOCK↓ See operating sequence; Figure 3 0 ns tSUCS Delay Time, CS/SHDN ↓ to DCLOCK↑ See operating sequence; Figure 3 30 ns NOTE: 11. During characterization, tDIS is measured from the release point with a 10pF load (see Figure 4) and the equivalent timing using the ADS1286 loading (3kΩ, 100pF) is calculated. Timing Specifications At fCLK = 200kHz , unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 8) TYP MAX (Note 8) UNITS FIGURE 3. SERIAL INTERFACE TIMING DIAGRAM tSUCS B10 B9B8B7B6B5B4B3B2 B1B0 B11 B10 B9B8 Null Bit Hi-Z Hi-Z Null Bit CS/SHDN DCLOCK DOUT tCSD tCYC POWER DOWN tSMPL tCONV tDATA Note: (1) After completing the data transfer, additional clocks applied while CS/SHDN is low will result in the previous data being retransmitted LSB-first, followed by indefinite transmission of zeros tSUCS B10 B9B8B7B6B5B4B3B2 B1B0 B11 B10 B9 B8 Null Bit Hi-Z Hi-Z CS/SHDN DCLOCK DOUT tCSD tCYC POWER DOWN tSMPL tCONV tDATA Note: (2) After completing the data transfer, additional clocks applied while CS/SHDN is low will result in indefinite transmission of zeros B1 B2 B3 B4 B5 B7 B6 B11 (MSB) B11 (MSB) (1) (2) FIGURE 4. EQUIVALENT LOAD CIRCUIT OUTPUT PIN CL 10pF +VCC 2.85k RL |
Số phần tương tự - ISL2671286 |
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Mô tả tương tự - ISL2671286 |
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