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SN74ACT2440FN bảng dữ liệu(PDF) 11 Page - Texas Instruments

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SN74ACT2440FN bảng dữ liệu(HTML) 11 Page - Texas Instruments

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SN74ACT2440
NuBus
™ INTERFACE CONTROLLER
SCHS010 – D3158, OCTOBER 1988 – REVISED JANUARY 1991
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
11
maximum block-transfer performance
As a master, the ’ACT2440 is capable of supporting the maximum block transfer rate of 37.6M-bytes/second
(one start cycle followed by 16 consecutive 100-ns data cycles). Figure 12 shows a more typical situation where
the slave controls the block transfer rate via the intermediate acknowledge signal (TM0). Note that the ’ACT2440
generates a data clock (DCLK) every clock cycle that TM0 is low. The final data cycle is a normal acknowledge
cycle.
In slave block transfer mode, the ’ACT2440 has been designed to provide a simple handshake between the
slave interim acknowledge (SIACK) input and the slave external request (SEREQ) output as shown in
Figure 15. Note that each data clock (DCLK) cycle goes high for 100 ns as a result of the simple handshake
between SIACK and SEREQ. In this simpler mode of operation, the maximum intermediate data transfer rate
when using the ’ACT2441 is 200 ns, which equates to approximately 20M-bytes/second.
NuBus
™ cycles from the parked position
As long as RQST remains unasserted, the bus owner is considered to be parked on the bus and may continue
to use the bus without the necessity of going through an arbitration contest in which it is the only contender. The
ANSI/IEEE 1196-1987 specification requires that as soon as another module drives the RQST line asserted,
an arbitration contest is started and the present bus owner (currently parked on the bus) must not begin another
transaction. The concept of bus parking reduces the average time needed to acquire the bus in systems with
a small number of active contenders.
When using the ’ACT2440 NuBus
™ controller from a parked position, the local board does not know if it remains
the NuBus
™ master and begins another transaction until the START signal has been generated. In other words,
just because the local board has taken MRDY and NREQ active (low), does not mean the ’ACT2440 continues
to own the bus and has generated a START cycle.
When the ’ACT2440 is in the parked position (NMSTR high) and no other masters are requesting the bus, a start
cycle is generated on the driving edge after NREQ and MRDY are taken active (low).
Figure 16 shows a situation where an old NuBus
™ master is initially parked on the bus and is attempting to issue
another START cycle (by taking MRDY low); but loses to a new master who is attempting to access data from
resources that are available on the old master’s board. In other words, the new master wins the bus and is trying
to use the old master as a slave. This situation is similar to the local resource conflict timing diagram shown in
Figure 6.
In Figure 16, the old master learns that it has lost the bus by detecting that NMSTR has gone inactive (low) during
the start cycle. The new master, which has just won the bus and has generated a start cycle, is attempting to
access data from the old master. The slave external request (SEREQ) output on the old master detects this
access request by going active (low) on the first sample edge after the start cycle. At this time, the old master
may want to take MRDY back to the inactive level (as shown in Figure 16) so that it has control of the START
signal after winning back the bus. If MRDY is not taken back to the inactive level (high) after losing the bus, then
the ’ACT2440 immediately issues a start cycle after the acknowledge cycle has been generated.
If the new master was directing the access cycle at a different slave, then the SEREQ output on the old master
would remain inactive (high) and the MRDY input on the old master can be kept low in order to generate a start
cycle as soon as the old master wins back the bus.
Notice from the timing diagram that if the old master takes MRDY low at the same time or in the following cycle,
then the old master loses to the new master.
If the old master takes MRDY low on the cycle before the new master takes RQST low, then the old master
retains the bus and completes its cycle.


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