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SN74ACT2440FN bảng dữ liệu(PDF) 6 Page - Texas Instruments |
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SN74ACT2440FN bảng dữ liệu(HTML) 6 Page - Texas Instruments |
6 / 33 page SN74ACT2440 NuBus ™ INTERFACE CONTROLLER SCHS010 – D3158, OCTOBER 1988 – REVISED JANUARY 1991 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 6 Terminal Functions (continued) NUBUS ™ STATUS SIGNALS PIN DESCRIPTION NAME NO. DESCRIPTION MDONE 46 Master done. This active-high output signal is asserted when the local board is the NuBus ™ master and the responding slave acknowledge (ACK) has been received. Once asserted, it remains asserted until MHOLD is unasserted. NACK 32 NuBus ™ acknowledge. This output is an inverted buffer version of the acknowledge signal (ACK). NCLK 39 Inverted NuBus ™ clock. This output signal is an inverted buffered version of the NuBus™ clock signal (CLK). NCLK 40 Buffered Nubus clock. This output signal is a buffered version of the NuBus ™ clock signal (CLK). NLOCK 45 NuBus ™ locked. This active-high output signal indicates to the local board that another master has generated an attention lock cycle and the local board is the requested slave. This output is asserted one clock after the NuBus ™ start cycle on the sample edge (high-low) of the NuBus ™ clock signal (CLK). NLOCK is active only during slave cycles. NLOCK is not active during master cycles. NLRST 33 NuBus ™ latched reset. This active-low output is a sychronized (2-level) version of the asynchronous NuBus™ reset signal (RESET). NLTM0 NLTN1 38 37 NuBus ™ latched transfered mode. These status signals are latched inverted versions of the NuBus™ TMx signals. They are doubled-latched to allow the local board to continue using TMx information. During NuBus ™ master cycles, the transfer code is latched on the sample edge of the start cycle. The transfer code remains latched until a slave responds with an acknowledge cycle. The transfer status is latched on the sample edge of the acknowledge cycle. The transfer status remains latched as long as MHOLD is held active (low). After MHOLD returns inactive, the transfer status remains latched until the next NuBus ™ start cycle. During slave cycles, the transfer code is latched on the sample edge of the cycle. The transfer code remains latched as long as SGNTA is held active (low). After SGNTA returns inactive, the transfer code remains latched until the next NuBus ™ start cycle. NMSTR 44 NuBus ™ master. This active-high output indicates to the local voaed that the local board has won arbitration and is now the NuBus ™ master. It is on the sample edge (high-to-low) of the NuBus™ clock signal (CLK) after winning arbitration. NMSTR remains asserted until the board loses mastership. NTM1 NTM1 36 35 NuBus ™ buffered transfer mode. These outputs are inverted buffered versions of the NuBus™ TMx lines (TM0, TM1). SEREQ 41 Slave external request. This active-low output indicates that the local board is being requested on the NuBus ™. The local board responds by driving slave grant access (SGNTA) active (low) when it is ready to service the request. In higher performance slave-only applications, SGNTA may be low going into the NuBus ™ cycle. NSTART 31 NuBus ™ start. This output is an inverted buffered version of the NuBus™ start signal (START). Table 1. Byte Decode Function Table TM0 A1 A0 BT0 BT1 BT2 BT3 TYPE OF CYCLE L L L L H H H Byte 0 L L H H L H H Byte 1 L H L H H L H Byte 2 L H H H H H L Byte 3 H L L L L L L Full Word H L H L L H H 1/2 Word 0 H H L L L L L Block H H H H H L L 1/2 Word 1 NOTE: TM1 = L indicates a write cycle. TM1 = H indicates a read cycle. |
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