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1 / 67 page SM470R1B1M-HT www.ti.com SPNS155F – SEPTEMBER 2009 – REVISED AUGUST 2012 16/32-BIT RISC FLASH MICROCONTROLLER 1 FEATURES – Asynchronous/Isosynchronous Modes – Two High-End CAN Controllers (HECC) 2 • High-Performance Static CMOS Technology – 32-Mailbox Capacity • SM470R1x 16/32-Bit RISC Core ( ARM7TDMI™) – Fully Compliant With CAN Protocol, – 60-MHz System Clock (Pipeline Mode) Version 2.0B – Independent 16/32-Bit Instruction Set – Five Inter-Integrated Circuit (I2C) Modules – Open Architecture With Third-Party Support – Multi-Master and Slave Interfaces – Built-In Debug Module – Up to 400 Kbps (Fast Mode) • Integrated Memory – 7- and 10-Bit Address Capability – 1M-Byte Program Flash • High-End Timer Lite (HET) – Two Banks With 16 Contiguous Sectors – 12 Programmable I/O Channels: – 64K-Byte Static RAM (SRAM) – 12 High-Resolution Pins – Memory Security Module (MSM) – High-Resolution Share Feature (XOR) – JTAG Security Module – High-End Timer RAM • Operating Features – 64-Instruction Capacity – Low-Power Modes: STANDBY and HALT • External Clock Prescale (ECP) Module – Industrial Temperature Range – Programmable Low-Frequency External • 470+ System Module Clock (CLK) – 32-Bit Address Space Decoding • 12-Channel, 10-Bit Multi-Buffered ADC – Bus Supervision for Memory/Peripherals (MibADC) – Digital Watchdog (DWD) Timer – 64-Word FIFO Buffer – Analog Watchdog (AWD) Timer – Single- or Continuous-Conversion Modes – Enhanced Real-Time Interrupt (RTI) – 1.55-µs Minimum Sample and Conversion – Interrupt Expansion Module (IEM) Time – System Integrity and Failure Detection – Calibration Mode and Self-Test Features – ICE Breaker • Flexible Interrupt Handling • Direct Memory Access (DMA) Controller • Expansion Bus Module (EBM) – 32 Control Packets and 16 Channels – Supports 8- and 16-Bit Expansion Bus • Zero-Pin Phase-Locked Loop (ZPLL)-Based Memory Interface Mappings Clock Module With Prescaler – 42 I/O Expansion Bus Pins – Multiply-by-4 or -8 Internal ZPLL Option • 46 Dedicated General-Purpose I/O (GIO) Pins – ZPLL Bypass Mode and 47 Additional Peripheral I/Os • Twelve Communication Interfaces: • Sixteen External Interrupts – Two Serial Peripheral Interfaces (SPIs) • On-Chip Scan-Base Emulation Logic, IEEE Standard 1149.1 (1) (JTAG) Test-Access Port – 255 Programmable Baud Rates • Available in KGD, HFQ and HKP Packages – Three Serial Communication Interfaces (SCIs) – 224 Selectable Baud Rates (1) The test-access port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture specification. Boundary scan is not supported on this device. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM). PRODUCTION DATA information is current as of publication date. Copyright © 2009–2012, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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