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SM320VC5416PGE16EP bảng dữ liệu(PDF) 7 Page - Texas Instruments

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tên linh kiện SM320VC5416PGE16EP
Giải thích chi tiết về linh kiện  SM320VC5416-EP Fixed-Point Digital Signal Processor
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Tables
v
July 2003
SGUS048
List of Tables
Table
Page
2−1
Terminal Assignments for the SM320VC5416GGU (144-Pin BGA Package)
3
. . . . . . . . . . . . . . . . .
2−2
Signal Descriptions
5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1
Standard On-Chip ROM Layout
12
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2
Processor Mode Status (PMST) Register Bit Fields
15
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3
Software Wait-State Register (SWWSR) Bit Fields
16
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4
Software Wait-State Control Register (SWCR) Bit Fields
17
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5
Bank-Switching Control Register (BSCR) Fields
18
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6
Bus Holder Control Bits
19
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−7
Sample Rate Input Clock Selection
23
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8
Clock Mode Settings at Reset
25
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−9
DMD Section of the DMMCRn Register
30
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−10
DMA Reload Register Selection
32
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−11
DMA Interrupts
33
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−12
DMA Synchronization Events
33
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−13
DMA Channel Interrupt Selection
33
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−14
CPU Memory-Mapped Registers
35
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−15
Peripheral Memory-Mapped Registers for Each DSP Subsystem
37
. . . . . . . . . . . . . . . . . . . . . . . . . .
3−16
McBSP Control Registers and Subaddresses
38
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−17
DMA Subbank Addressed Registers
39
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−18
Interrupt Locations and Priorities
41
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−1
Thermal Resistance Characteristics
46
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−2
Input Clock Frequency Characteristics
46
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−3
Clock Mode Pin Settings for the Divide-By-2 and By Divide-by-4 Clock Options
47
. . . . . . . . . . . . . .
5−4
Divide-By-2 and Divide-by-4 Clock Options Timing Requirements
48
. . . . . . . . . . . . . . . . . . . . . . . . . .
5−5
Divide-By-2 and Divide-by-4 Clock Options Switching Characteristics
48
. . . . . . . . . . . . . . . . . . . . . . .
5−6
Multiply-By-N Clock Option Timing Requirements
49
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−7
Multiply-By-N Clock Option Switching Characteristics
49
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−8
Memory Read Timing Requirements
50
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−9
Memory Read Switching Characteristics
50
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−10
Memory Write Switching Characteristics
52
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−11
I/O Read Timing Requirements
53
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−12
I/O Read Switching Characteristics
53
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−13
I/O Write Switching Characteristics
54
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−14
Ready Timing Requirements for Externally Generated Wait States
55
. . . . . . . . . . . . . . . . . . . . . . . . .
5−15
Ready Switching Characteristics for Externally Generated Wait States
55
. . . . . . . . . . . . . . . . . . . . . .
5−16
HOLD and HOLDA Timing Requirements
60
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−17
HOLD and HOLDA Switching Characteristics
60
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−18
Reset, BIO, Interrupt, and MP/MC Timing Requirements
62
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−19
Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics
64
. . . .
5−20
External Flag (XF) and TOUT Switching Characteristics
65
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


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