công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
SM320VC5416-EP bảng dữ liệu(PDF) 5 Page - Texas Instruments |
|
|
SM320VC5416-EP bảng dữ liệu(HTML) 5 Page - Texas Instruments |
5 / 94 page Figures iii July 2003 SGUS048 List of Figures Figure Page 2−1 144-Ball GGU MicroStar BGA (Bottom View) 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2 144-Pin PGE Low-Profile Quad Flatpack (Top View) 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1 SM320VC5416-EP Functional Block Diagram 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2 Program and Data Memory Map 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−3 Extended Program Memory Map 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−4 Processor Mode Status (PMST) Register 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5 Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h] 16 . . . 3−6 Software Wait-State Control Register (SWCR) [MMR Address 002Bh] 17 . . . . . . . . . . . . . . . . . . . . . . . 3−7 Bank-Switching Control Register (BSCR) [MMR Address 0029h] 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8 Host-Port Interface — Nonmultiplexed Mode 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−9 HPI Memory Map 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−10 Multichannel Control Registers (MCR1 and MCR2) 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−11 Pin Control Register (PCR) 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−12 Nonconsecutive Memory Read and I/O Read Bus Sequence 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−13 Consecutive Memory Read Bus Sequence (n = 3 reads) 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−14 Memory Write and I/O Write Bus Sequence 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−15 DMA Transfer Mode Control Register (DMMCRn) 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−16 On-Chip DMA Memory Map for Program Space (DLAXS = 0 and SLAXS = 0) 30 . . . . . . . . . . . . . . . . 3−17 On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0) 31 . . . . . . . . . . . . . 3−18 DMPREC Register 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−19 General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch] 34 . . . . . . . . . . . . . . . . . . . . 3−20 General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh] 34 . . . . . . . . . . . . . . . . . . . . . 3−21 Device ID Register (CSIDR) [MMR Address 003Eh] 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−22 IFR and IMR 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−1 3.3-V Test Load Circuit 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−2 Internal Divide-by-Two Clock Option With External Crystal 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−3 External Divide-by-Two Clock Timing 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−4 Multiply-by-One Clock Timing 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−5 Nonconsecutive Mode Memory Reads 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−6 Consecutive Mode Memory Reads 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−7 Memory Write (MSTRB = 0) 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−8 Parallel I/O Port Read (IOSTRB = 0) 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−9 Parallel I/O Port Write (IOSTRB = 0) 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−10 Memory Read With Externally Generated Wait States 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−11 Memory Write With Externally Generated Wait States 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−12 I/O Read With Externally Generated Wait States 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−13 I/O Write With Externally Generated Wait States 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
Số phần tương tự - SM320VC5416-EP |
|
Mô tả tương tự - SM320VC5416-EP |
|
|
Link URL |
Chính sách bảo mật |
ALLDATASHEET.VN |
Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |