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SM320VC5409GGU10EP bảng dữ liệu(PDF) 2 Page - Texas Instruments |
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SM320VC5409GGU10EP bảng dữ liệu(HTML) 2 Page - Texas Instruments |
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2 / 78 page  SM320VC5409EP FIXEDPOINT DIGITAL SIGNAL PROCESSOR SGUS046 − JULY 2003 2 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Table of Contents Internal Oscillator with External Crystal 39 . . . . . . . . Divide-by-Two/Divide-by-Four Clock Option 40 . . . . Multiply-by-N Clock Option 41 . . . . . . . . . . . . . . . . . . . Memory and Parallel I/O Interface Timing 42 . . . . . . Timing For Externally Generated Wait States 48 . . . HOLD and HOLDA Timings 52 . . . . . . . . . . . . . . . . . . Reset, BIO, Interrupt, and MP/MC Timings 54 . . . . . Instruction Acquisition (IAQ), Interrupt Acknowledge (IACK), External Flag (XF), and TOUT Timings 56 . . . . . . . . . . . . . . . . . . . . . Multichannel Buffered Serial Port Timing 58 . . . . . . . HPI8 Timing 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HPI16 Timing 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mechanical Data 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . Description 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Terminal Functions 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-chip Peripherals 14 . . . . . . . . . . . . . . . . . . . . . . . . . . Memory-mapped Registers 29 . . . . . . . . . . . . . . . . . . . . McBSP Control Registers And Subaddresses 32 . . . . DMA Subbank Addressed Registers 32 . . . . . . . . . . . . Interrupts 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Documentation Support 36 . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings 37 . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions 37 . . . . . . . . . . . Electrical Characteristics 38 . . . . . . . . . . . . . . . . . . . . . . Parameter Measurement Information 38 . . . . . . . . . . . . description The SM320VC5409-EP fixed-point, digital signal processor (DSP) (hereafter referred to as the ’5409 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set. Separate program and data spaces allow simultaneous access to program instructions and data, providing the high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. In addition, the ’5409 includes the control mechanisms to manage interrupts, repeated operations, and function calls. ORDERING INFORMATION TA PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING −40 °C to 100°C BGA − GGU SM320VC5409GGU10EP M5409GGUEP † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. |
Số phần tương tự - SM320VC5409GGU10EP |
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Mô tả tương tự - SM320VC5409GGU10EP |
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