 |
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
|
công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
SM320VC5409-EP bảng dữ liệu(PDF) 5 Page - Texas Instruments |
|
||||||||||||||||||||||||||||||
SM320VC5409-EP bảng dữ liệu(HTML) 5 Page - Texas Instruments |
|
|
5 / 78 page  SM320VC5409EP FIXEDPOINT DIGITAL SIGNAL PROCESSOR SGUS046 − JULY 2003 5 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 terminal functions The ’5409 signal descriptions table lists each pin name, function, and operating mode(s) for the ’5409 device. Some of the ’5409 pins can be configured for one of two functions; a primary function and a secondary function. The names of these pins in secondary mode are shaded in grey in the following table. Terminal Functions TERMINAL NAME INTERNAL I/O† DESCRIPTION TERMINAL NAME PIN STATE I/O† DESCRIPTION DATA SIGNALS A22 (MSB) A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 (LSB) Bus holders available (A15−A0) O/Z Parallel address bus A22 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The lower sixteen address pins (A15 to A0) are multiplexed to address all external memory (program, data) or I/O while the upper seven address pins (A22 to A16) are only used to address external program space. These pins are placed in the high-impedance state when the hold mode is enabled, or when OFF is low. D15 (MSB) D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (LSB) Bus holders available I/O/Z Parallel data bus D15 (MSB) through D0 (LSB). The sixteen data pins (D15 to D0) are multiplexed to transfer data between the core CPU and external data/program memory or I/O devices. The data bus is placed in the high-impedance state when not outputting or when RS or HOLD is asserted. The data bus also goes into the high-impedance state when OFF is low. The data bus has bus holders to reduce the static power dissipation caused by floating, unused pins. These bus holders also eliminate the need for external bias resistors on unused pins. When the data bus is not being driven by the ’5409, the bus holders keep the pins at the previous logic level. The data bus holders on the ’5409 are disabled at reset and can be enabled/disabled via the BH bit of the bank-switching control register (BSCR). INITIALIZATION, INTERRUPT, AND RESET OPERATIONS IACK O/Z Interrupt acknowledge signal. IACK indicates receipt of an interrupt and that the program counter is fetching the interrupt vector location designated by A15−A0. IACK also goes into the high-impedance state when OFF is low. INT0 INT1 INT2 INT3 Schmitt trigger I External user interrupts. INT0−INT3 are prioritized and are maskable by the interrupt mask register and the interrupt mode bit. INT0 −INT3 can be polled and reset by way of the interrupt flag register. † I = Input, O = Output, Z = High-impedance, S = Supply |
Số phần tương tự - SM320VC5409-EP |
|
Mô tả tương tự - SM320VC5409-EP |
|
|
Link URL |
| Chính sách bảo mật |
| ALLDATASHEET.VN |
| Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Vietnamese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
