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SM32C6414EGLZ50AEP bảng dữ liệu(PDF) 1 Page - Texas Instruments |
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SM32C6414EGLZ50AEP bảng dữ liệu(HTML) 1 Page - Texas Instruments |
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1 / 93 page  1 Introduction 1.1 Features SM320C6414-EP, SM320C6415-EP, SM320C6416-EP FIXED-POINT DIGITAL SIGNAL PROCESSORS www.ti.com SGUS043D – MAY 2003 – REVISED SEPTEMBER 2008 1280M-Byte Addressable External Memory • Highest-Performance Fixed-Point Digital Signal Processors (DSPs) • Enhanced Direct Memory Access (EDMA) – 2-ns Instruction Cycle Time Controller (64 Independent Channels) – 500-MHz Clock Rate • Host-Port Interface (HPI) – Eight 32-Bit Instructions/Cycle – User-Configurable Bus Width (32/16 Bit) – 28 Operations/Cycle • 32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface – 4000 MIPS Conforms to PCI Specification 2.2 – Fully Software Compatible With C62x™ (C6415/C6416) – C6414/15/16 Devices Pin Compatible – Three PCI Bus Address Registers • VelociTI.2™ Extensions to VelociTI™ – Four-Wire Serial EEPROM Interface Advanced Very Long Instruction Word (VLIW) – PCI Interrupt Request Under DSP Program TMS320C64x™ DSP Core Control – Eight Highly Independent Functional Units – DSP Interrupt Via PCI I/O Cycle With VelociTI.2 Extensions With Six ALUs • Three Multichannel Buffered Serial Ports and Two Multipliers (McBSPs) – Nonaligned Load-Store Architecture – Direct Interface to T1/E1, MVIP, and SCSA – 64 32-Bit General-Purpose Registers Framers – Instruction Packing Reduces Code Size – Up to 256 Channels Each – All Instructions Conditional – ST Bus Switching, AC97 Compatible • Instruction Set Features – Serial Peripheral Interface (SPI) Compatible – Byte-Addressable (8-/16-/32-/64-Bit Data) (Motorola) – 8-Bit Overflow Protection • Three 32-Bit General-Purpose Timers – Bit-Field Extract, Set, Clear • Universal Test and Operations Physical Layer – Normalization, Saturation, Bit Counting (PHY) Interface for ATM (UTOPIA) – VelociTI.2 Increased Orthogonality (C6415/C6416) • Viterbi Decoder Coprocessor (VCP) (C6416) – UTOPIA Level-2 Slave ATM Controller – Supports Over 500 7.95-Kbps Adaptive – 8-Bit Transmit and Receive Operations up Multi-Rate (AMR) to 50 MHz per Direction – Programmable Code Parameters – User-Defined Cell Format up to 64 Bytes • Turbo Decoder Coprocessor (TCP) (C6416) • 16 General-Purpose I/O (GPIO) Pins – Supports up to Six 2-Mbps 3GPP • Flexible Phase-Locked Loop (PLL) Clock (Six Iterations) Generator – Programmable Turbo Code and Decoding • IEEE Std 1149.1 (JTAG(1)) Boundary Scan Parameters Compatible • L1/L2 Memory Architecture • 532-Pin Ball Grid Array (BGA) Package (GLZ – 128K-Bit (16K-Byte) L1P Program Cache Suffix), 0.8-mm Ball Pitch – 128K-Bit (16K-Byte) L1D Data Cache • 0.13-µm/6-Level Metal Process (CMOS) – 8M-Bit (1024K-Byte) L2 Unified Mapped • 3.3-V I/Os, 1.25-V Internal (500 MHz) RAM/Cache (1) IEEE Std 1149.1-1990 Standard Test-Access Port and • Two External Memory Interfaces (EMIFs) for Boundary Scan Architecture Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. PRODUCTION DATA information is current as of publication date. Copyright © 2003–2008, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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