SMJ320C50/SMQ320C50

DIGITAL SIGNAL PROCESSOR

SGUS020B -- JUNE 1996 -- REVISED SEPTEMBER 2001

11

POST OFFICE BOX 1443

PARAMETER MEASUREMENT INFORMATION

Tester Pin

Electronics

Output

Under

Test

50 Ω

Where:

=

2.0 mA (all outputs)

=

300 μA (all outputs)

=1.5 V

=

80 pF typical load circuit capacitance

Figure 1. Test Load Circuit

signal transition levels

Transistor-to-transistor logic (TTL) output levels are driven to a minimum logic-high level of 2.4 V and to a

maximum logic-low level of 0.6 V. Figure 2 shows the TTL-level outputs.

0.6 V

1V

2V

2.4 V

Figure 2. TTL-Level Outputs

TTL-output transition times are specified as follows:

D

For a high-to-low transition, the level at which the output is said to be no longer high is 2 V, and the level

at which the output is said to be low is 1 V.

D

For a low-to-high transition, the level at which the output is said to be no longer low is 1 V, and the level

at which the output is said to be high is 2 V.

Figure 3 shows the TTL-level inputs.

2.2 V

0.6 V

Figure 3. TTL-Level Inputs

TTL-compatible input transition times are specified as follows:

D

For a high-to-low transition on an input signal, the level at which the input is said to be no longer high

is 2 V, and the level at which the input is said to be low is 0.8 V.

D

For a low to high transisiton on an input signal, the level at which the input is said to be no longer low

is 0.8 V, and the level at which the input is said to be high is 2 V.