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SM320C6201-EP bảng dữ liệu(PDF) 9 Page - Texas Instruments |
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SM320C6201-EP bảng dữ liệu(HTML) 9 Page - Texas Instruments |
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9 / 59 page  SM320C6201-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SGUS041A -- MAY 2003 -- REVISED JANUARY 2004 9 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251--1443 Signal Descriptions SIGNAL PIN NO. TYPE† DESCRIPTION SIGNAL NAME GJC TYPE† DESCRIPTION CLOCK/PLL CLKIN C10 I Clock Input CLKOUT1 AF22 O Clock output at full device speed CLKOUT2 AF20 O Clock output at half of device speed CLKMODE1 C6 I Clock mode selects • Selects whether the CPU clock frequency =input clock frequency x4 or x1 CLKMODE0 C5 I • Selects whether the CPU clock frequency = input clock frequency x4 or x1 For more details on the GJC and GJL CLKMODE pins and the PLL multiply factors, see the Clock PLL section of this data sheet. PLLFREQ3 A9 PLL frequency range (3, 2, and 1) PLLFREQ2 D11 I PLL frequency range (3, 2, and 1) • The target range for CLKOUT1 frequency is determined by the 3-bit value of the PLLFREQ1 B10 I The target range for CLKOUT1 frequency is determined by the 3 bit value of the PLLFREQ pins. PLLV‡ D12 A§ PLL analog VCC connection for the low-pass filter PLLG‡ C12 A§ PLL analog GND connection for the low-pass filter PLLF A11 A§ PLL low-pass filter connection to external components and a bypass capacitor JTAG EMULATION TMS L3 I JTAG test port mode select (features an internal pullup) TDO W2 O/Z JTAG test port data out TDI R4 I JTAG test port data in (features an internal pullup) TCK R3 I JTAG test port clock TRST T1 I JTAG test port reset (features an internal pulldown) EMU1 Y1 I/O/Z Emulation pin 1, pullup with a dedicated 20-kΩ resistor¶ EMU0 W3 I/O/Z Emulation pin 0, pullup with a dedicated 20-kΩ resistor¶ RESET AND INTERRUPTS RESET K2 I Device reset NMI L2 I Nonmaskable interrupt • Edge-driven (rising edge) EXT_INT7 U3 External interrupts EXT_INT6 V2 I External interrupts • Edge-driven EXT_INT5 W1 I • Edge-driven • Polarity independently selected via the external interrupt polarity register bits (EXTPOL [3 0]) EXT_INT4 U4 y p y p p y g (EXTPOL.[3:0]) IACK Y2 O Interrupt acknowledge for all active interrupts serviced by the CPU INUM3 AA1 INUM2 W4 O Active interrupt identification number • Valid during IACK for all active interrupts (not just external) INUM1 AA2 O • Valid during IACK for all active interrupts (not just external) • Encoding order follows the interrupt-service fetch-packet ordering INUM0 AB1 • Encoding order follows the interrupt-service fetch-packet ordering LITTLE ENDIAN/BIG ENDIAN LENDIAN H3 I If high, LENDIAN selects little-endian byte/half-word addressing order within a word If low, LENDIAN selects big-endian addressing POWER-DOWN STATUS PD D3 O Power-down mode 2 or 3 (active if high) † I = Input, O = Output, Z = High Impedance, S = Supply Voltage, GND = Ground ‡ PLLV and PLLG are not part of external voltage supply or ground. See the clock PLL section for information on how to connect these pins. § A = Analog Signal (PLL Filter) ¶ For emulation and normal operation, pull up EMU1 and EMU0 with a dedicated 20-kΩ resistor. For boundary scan, pull down EMU1 and EMU0 with a dedicated 20-kΩ resistor. |
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