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Giải thích chi tiết về linh kiện  FLOATING-POINT DIGITAL SIGNAL PROCESSORS
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SM320C6712EP, SM320C6712CEP, SM320C6712DEP
FLOATINGPOINT DIGITAL SIGNAL PROCESSORS
SGUS055 − SEPTEMBER 2004
4
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
description
The 320C67x
 DSPs (including the SM320C6712-EP, SM320C6712C-EP, SM320C6712D-EP devices) are
members of the floating-point DSP family in the TMS320C6000
 DSP platform. The C6712, C6712C, and
C6712D devices are based on the high-performance, advanced very-long-instruction-word (VLIW) architecture
developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction
applications.
With performance of up to 1000 million floating-point operations per second (MFLOPS) at a clock rate of
167 MHz, the C6712C/C6712D device is the lowest-cost DSP in the C6000
 DSP platform. The
C6712C/C6712D DSP possesses the operational flexibility of high-speed controllers and the numerical
capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight
highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two
fixed-point ALUs, and two floating-/fixed-point multipliers. The C6712C/C6712D can produce two MACs per
cycle for a total of 300 MMACS.
With performance of up to 600 million floating-point operations per second (MFLOPS) at a clock rate of
100 MHz, the C6712 device also offers cost-effective solutions to high-performance DSP programming
challenges. The C6712 DSP possesses the operational flexibility of high-speed controllers and the numerical
capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight
highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two
fixed-point ALUs, and two floating-/fixed-point multipliers. The C6712 can produce two multiply-accumulates
(MACs) per cycle for a total of 200 million MACs per second (MMACS).
The C6712/C6712C/C6712D uses a two-level cache-based architecture and has a powerful and diverse set
of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache
(L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory
space that is shared between program and data space. L2 memory can be configured as mapped memory,
cache, or combinations of the two. The peripheral set includes two multichannel buffered serial ports (McBSPs),
two general-purpose timers, and a glueless 16-bit external memory interface (EMIF) capable of interfacing to
SDRAM, SBSRAM, and asynchronous peripherals. The C6712C device also includes a dedicated
general-purpose input/output (GPIO) peripheral module.
The C6712/C6712C/C6712D DSPs also have application-specific hardware logic, on-chip memory, and
additional on-chip peripherals.
The C6712/C6712C/C6712D has a complete set of development tools which includes: a new C compiler, an
assembly optimizer to simplify programming and scheduling, and a Windows
 debugger interface for visibility
into source code execution.
TMS320C6000 and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
† Throughout the remainder of this document, the SM320C6712-EP, SM320C6712C-EP, and SM320C6712D-EP shall be referred to as 320C67x
or C67x where generic, and where specific, their individual full device part numbers will be used or abbreviated as C6712, C6712C, C6712D,
12, 12C, or 12D, etc.


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