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MCP2210-I-SO bảng dữ liệu(PDF) 9 Page - Microchip Technology |
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MCP2210-I-SO bảng dữ liệu(HTML) 9 Page - Microchip Technology |
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9 / 82 page  2011 Microchip Technology Inc. DS22288A-page 9 MCP2210 2.0 MCP2210 FUNCTIONAL DESCRIPTION The MCP2210 uses NVRAM to store relevant chip settings. These settings are loaded by the chip during the power-up process and they are used for GP designation and SPI transfers. The NVRAM settings at power-up (or Reset) are loaded into the RAM portion of the chip and they can be altered through certain USB commands. This is very useful since it allows dynamic reconfiguring of the GPs or SPI transfer parameters. A practical example to illustrate this mechanism is a system which uses at least two SPI slave chips and the GPs in the MCP2210 for various GPIO purposes. The default SPI settings might be ok for one of the SPI slave chips, but not for the 2nd. At first, the PC application will make an SPI transfer to the first chip, using the NVRAM copy of the SPI settings. Then, by sending a certain USB command, the SPI transfer settings residing in RAM will be altered in order to fit the SPI transfer requirements of the second chip. Also, if the altered SPI transfer settings are needed to be the default power-up (or Reset) settings for SPI, the user can send a series of USB commands in order to store the current (RAM) SPI settings into NVRAM. In this way, these new settings will be the power-up default SPI settings. The NVRAM settings and EEPROM contents can be protected by password access means, or they can be permanently locked without any possible further modification. 2.1 MCP2210 NVRAM Settings The chip settings that can be stored in the NVRAM area are as follows: • SPI transfer parameters: - SPI bit rate - SPI mode - Idle Chip Select values - Active Chip Select values - SPI transfer configurable delays - Number of bytes to read/write for the given SPI transfer • GP designation: -GPIO - Chip Select - Dedicated function • GPIO default direction (applies only to those GPs designated as GPIOs) • GPIO default output value (applies only to those GPs designated as output GPIOs) • Chip mode flags: - Remote wake-up capability - External Interrupt Pin mode (applies only when GP6 is designated for this function) - SPI bus release enable/disable – enable/ disable the release of the SPI bus when there is no SPI transfer (useful when more than one SPI master on the bus) • NVRAM Access mode: - Full access (no protection – factory default) - Password protection - Permanently locked • Password (relevant when password protection mechanism is active) The specified settings are loaded at power-up or Reset moments, and they can be altered through certain USB commands. When a NVRAM conditional access method is already in place, such as password protection, the NVRAM settings modification is permitted only when the user has supplied the correct password for the chip. The RAM settings can be altered even when a password protection or permanent lock mechanism are in place. This allows the user to communicate with various SPI slave chips without knowing the password, but it will not allow the modification of the power-up default settings in NVRAM. 2.2 SPI Transfers The MCP2210 device provides advanced SPI communication features such as configurable delays and multiple Chip Select support. The configurable delays are related to certain aspects of the SPI transfer: • The delay between the assertion of Chip Select(s) and the first data byte (Figure 2-1) FIGURE 2-1: CHIP SELECT TO DATA DELAY TCS2DATA CS SCK MOSI MISO |
Số phần tương tự - MCP2210-I-SO |
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Mô tả tương tự - MCP2210-I-SO |
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