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ADS7828EBIPWRQ1 bảng dữ liệu(PDF) 8 Page - Texas Instruments |
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ADS7828EBIPWRQ1 bảng dữ liệu(HTML) 8 Page - Texas Instruments |
8 / 22 page ADS7828-Q1 SBAS456A – DECEMBER 2008 – REVISED OCTOBER 2009.......................................................................................................................................... www.ti.com SWITCHING CHARACTERISTICS (1) (2) +VDD = 2.7 V, over operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER TEST CONDITIONS MIN MAX UNIT Standard mode 100 kHz Fast mode 400 fSCL SCL clock frequency Cb = 100 pF max 3.4 High-speed mode MHz Cb = 400 pF max 1.7 Standard mode 4.7 Bus free time between Stop and Start tBUF μs conditions Fast mode 1.3 Standard mode 4 μs tHD; STA Hold time (repeated) Start condition Fast mode 600 ns High-speed mode 160 Standard mode 4.7 μs Fast mode 1.3 tlow Low period of the SCL clock Cb = 100 pF max 160 High-speed mode(3) ns Cb = 400 pF max 320 Standard mode 4 μs Fast mode 600 thigh High period of the SCL clock Cb = 100 pF max 60 ns High-speed mode(3) Cb = 400 pF max 120 Standard mode 4.7 μs tSU; STA Setup time for a repeated Start condition Fast mode 600 ns High-speed mode 160 Standard mode 250 tSU; DAT Data setup time Fast mode 100 ns High-speed mode 10 Standard mode 0 3.45 μs Fast mode 0 0.9 tHD; DAT Data hold time Cb = 100 pF max 0 82 High-speed mode(3) (4) ns Cb = 400 pF max 0 162 Standard mode 1000 Fast mode 20 + 0.1Cb 300 trCL Rise time of SCL signal ns Cb = 100 pF max 10 40 High-speed mode(3) Cb = 400 pF max 20 80 Standard mode 1000 Fast mode 20 + 0.1Cb 300 Rise time of SCL signal after a repeated Start trCL1 ns condition and after an acknowledge bit Cb = 100 pF max 10 80 High-speed mode(3) Cb = 400 pF max 20 160 Standard mode 300 Fast mode 20 + 0.1Cb 300 tfCL Fall time of SCL signal ns Cb = 100 pF max 10 40 High-speed mode(3) Cb = 400 pF max 20 80 Standard mode 1000 Fast mode 20 + 0.1Cb 300 trDA Rise time of SDA signal ns Cb = 100 pF max 10 80 High-speed mode(3) Cb = 400 pF max 20 160 (1) All values referred to VIH(MIN) and VIL(MAX) levels. (2) Not production tested, except for the parameter tHD; DAT, data hold time, high-speed mode, Cb = 100 pF max. (3) For bus line loads (CB) between 100 pF and 400 pF, the timing parameters must be linearly interpolated. (4) A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time. 8 Submit Documentation Feedback Copyright © 2008–2009, Texas Instruments Incorporated Product Folder Link(s): ADS7828-Q1 |
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