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ADS7822IDGKRQ1 bảng dữ liệu(PDF) 11 Page - Texas Instruments

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THEORY OF OPERATION
ANALOG INPUT
REFERENCE INPUT
ADS7822-Q1
www.ti.com .................................................................................................................................................................................................. SGLS299 – MARCH 2009
The ADS7822 is a classic successive approximation register (SAR) A/D converter. The architecture is based on
capacitive redistribution that inherently includes a sample/hold function. The converter is fabricated on a 0.6
µ
CMOS process. The architecture and process allow the ADS7822 to acquire and convert an analog signal at up
to 200,000 conversions per second while consuming very little power.
The ADS7822 requires an external reference, an external clock, and a single power source (VCC). The external
reference can be any voltage between 50 mV and VCC. The value of the reference voltage directly sets the range
of the analog input. The reference input current depends on the conversion rate of the ADS7822.
The external clock can vary between 10 kHz (625 Hz throughput) and 3.2 MHz (200 kHz throughput). The duty
cycle of the clock is essentially unimportant as long as the minimum high and low times are at least 400 ns for a
supply range between 2.7 V to 3.6 V, or 125 ns for a supply range between 4.75 V to 5.25 V. The minimum clock
frequency is set by the leakage on the capacitors internal to the ADS7822.
The analog input is provided to two input pins: +In and –In. When a conversion is initiated, the differential input
on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are
disconnected from any internal function.
The digital result of the conversion is clocked out by the DCLOCK input and is provided serially, most significant
bit first, on the DOUT pin. The digital data that is provided on the DOUT pin is for the conversion currently in
progress—there is no pipeline delay. It is possible to continue to clock the ADS7822 after the conversion is
complete and to obtain the serial data least significant bit first. See the Digital Interface section for more
information.
The +In and –In input pins allow for a pseudo-differential input signal. Unlike some converters of this type, the
–In input is not resampled later in the conversion cycle. When the converter goes into the hold mode, the voltage
difference between +In and –In is captured on the internal capacitor array.
The range of the –In input is limited to –0.2 V to 1 V. Because of this, the differential input can be used to reject
only small signals that are common to both inputs. Thus, the –In input is best used to sense a remote signal
ground that may move slightly with respect to the local ground potential.
The input current on the analog inputs depends on a number of factors: sample rate, input voltage, source
impedance, and power-down mode. Essentially, the current into the ADS7822 charges the internal capacitor
array during the sample period. After this capacitance has been fully charged, there is no further input current.
The source of the analog input voltage must be able to charge the input capacitance (25 pF) to a 12-bit settling
level within 1.5 clock cycles. When the converter goes into the hold mode or while it is in the power-down mode,
the input impedance is greater than 1 G
Ω.
Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the
–In input should not drop below GND – 200 mV or exceed GND + 1 V. The +In input should always remain within
the range of GND – 200 mV to VCC + 200 mV. Outside of these ranges, the converter linearity may not meet
specifications.
The external reference sets the analog input range. The ADS7822 operates with a reference in the range of
50 mV to VCC. There are several important implications of this.
As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This is
often referred to as the LSB (least significant bit) size and is equal to the reference voltage divided by 4096. This
means that any offset or gain error inherent in the A/D converter will appear to increase, in terms of LSB size, as
the reference voltage is reduced.
The noise inherent in the converter will also appear to increase with lower LSB size. With a 2.5-V reference, the
internal noise of the converter typically contributes only 0.32 LSB peak-to-peak of potential error to the output
code. When the external reference is 50 mV, the potential error contribution from the internal noise will be 50
times larger—16 LSBs. The errors due to the internal noise are gaussian in nature and can be reduced by
averaging consecutive conversion results.
Copyright © 2009, Texas Instruments Incorporated
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