ADF4360-9

Data Sheet

Rev. B | Page 2 of 24

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

Transistor Count........................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Circuit Description......................................................................... 10

Reference Input Section............................................................. 10

N Counter.................................................................................... 10

R Counter .................................................................................... 10

PFD and Charge Pump.............................................................. 10

Lock Detect ................................................................................. 10

Input Shift Register .................................................................... 10

VCO ............................................................................................. 11

Output Stage................................................................................ 12

DIVOUT Stage............................................................................ 12

Latch Structure ........................................................................... 13

Power-Up..................................................................................... 17

Control Latch .............................................................................. 18

N Counter Latch......................................................................... 19

R Counter Latch ......................................................................... 19

Applications..................................................................................... 20

Choosing the Correct Inductance Value................................. 20

Encode Clock for ADC.............................................................. 20

GSM Test Clock .......................................................................... 21

Interfacing ................................................................................... 22

PCB Design Guidelines for Chip Scale Package .................... 22

Output Matching ........................................................................ 23

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 24

REVISION HISTORY

2/12—Rev. A to Rev. B

Added EPAD Note............................................................................ 7

Updated Outline Dimensions ....................................................... 24

Changes to Ordering Guide .......................................................... 24

3/08—Rev. 0 to Rev. A

Changes to Table 1 ........................................................................... 3

Changes to Figure 23...................................................................... 14

Changes to Output Matching Section.......................................... 23

1/08—Revision 0: Initial Version