ADCMP600/ADCMP601/ADCMP602

Rev. A | Page 5 of 16

TIMING INFORMATION

Figure 2 illustrates the ADCMP600/ADCMP601/ADCMP602 latch timing relationships. Table 2 provides definitions of the terms shown

in Figure 2.

1.1V

50%

DIFFERENTIAL

INPUT VOLTAGE

LATCH ENABLE

Q OUTPUT

Figure 2. System Timing Diagram

Table 2. Timing Descriptions

Symbol

Timing

Description

t

PDH

Input to output high delay

Propagation delay measured from the time the input signal crosses the reference (± the

input offset voltage) to the 50% point of an output low-to-high transition.

t

PDL

Input to output low delay

Propagation delay measured from the time the input signal crosses the reference (± the

input offset voltage) to the 50% point of an output high-to-low transition.

t

PLOH

Latch enable to output high delay

Propagation delay measured from the 50% point of the latch enable signal low-to-high

transition to the 50% point of an output low-to-high transition.

t

PLOL

Latch enable to output low delay

Propagation delay measured from the 50% point of the latch enable signal low-to-high

transition to the 50% point of an output high-to-low transition.

t

H

Minimum hold time

Minimum time after the negative transition of the latch enable signal that the input signal

must remain unchanged to be acquired and held at the outputs.

t

PL

Minimum latch enable pulse width

Minimum time that the latch enable signal must be high to acquire an input signal change.

t

S

Minimum setup time

Minimum time before the negative transition of the latch enable signal occurs that an

input signal change must be present to be acquired and held at the outputs.

t

R

Output rise time

Amount of time required to transition from a low to a high output as measured at the 20%

and 80% points.

t

F

Output fall time

Amount of time required to transition from a high to a low output as measured at the 20%

and 80% points.

V

OD

Voltage overdrive

Difference between the input voltages V