Data Sheet

ADF4360-7

Rev. B | Page 7 of 28

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADF4360-7

TOP VIEW

(Not to Scale)

CPGND

1

AGND

3

DATA

18

CLK

17

16

DGND

15

14

13

PIN 1

IDENTIFIER

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Function

1

CPGND

Charge Pump Ground. This is the ground return path for the charge pump.

2

Analog Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane should be

3, 8, 11, 22

AGND

Analog Ground. This is the ground return path of the prescaler and VCO.

4

VCO Output. The output level is programmable from −5 dBm to −14 dBm. See the Output Matching section for a

description of the various output stages.

5

VCO Complementary Output. The output level is programmable from −5 dBm to −14 dBm. See the Output Matching

section for a description of the various output stages.

6

Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane should

7

Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CP output voltage.

9

L1

An external inductor to AGND should be connected to this pin to set the ADF4360-7 output frequency. L1 and L2 need

to be the same value. For inductances greater than 3.3 nH, a 470 Ω resistor should be added in parallel to AGND.

10

L2

An external inductor to AGND should be connected to this pin to set the ADF4360-7 output frequency. L1 and L2 need

to be the same value. For inductances greater than 3.3 nH, a 470 Ω resistor should be added in parallel to AGND.

12

Internal Compensation Node. This pin must be decoupled to ground with a 10 nF capacitor.

13

Connecting a resistor between this pin and CPGND sets the maximum charge pump output current for the synthesizer. The

SET

CPmax

R

I

11.75

=

14

15

DGND

Digital Ground.

16

(see Figure 16). This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.

17

CLK

Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit

shift register on the CLK rising edge. This input is a high impedance CMOS input.

18

DATA

Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high

impedance CMOS input.

19

LE

Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, and

the relevant latch is selected using the control bits.

20

MUXOUT

This multiplexer output lets either the lock detect, the scaled RF, or the scaled reference frequency be accessed externally.

21

Digital Power Supply. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the digital ground plane should be

23

CE

Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode. Taking

the pin high powers up the device depending on the status of the power-down bits.

24

CP

EP

Exposed Pad. The exposed pad must be connected to AGND.