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ADV7533BCBZ-RL bảng dữ liệu(PDF) 6 Page - Analog Devices |
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6 / 12 page ADV7533 Rev. 0 | Page 6 of 12 The power supply noise sensitivity of the ADV7533 is frequency dependent. Therefore, the maximum noise limit for the PVDD is specified in mV rms vs. frequency (see Figure 2). 70 60 50 40 30 20 10 0 1 10 100 1k 10k FREQUENCY (Hz) Figure 2. PVDD Maximum Noise Limit MIPI/DSI SPECIFICATIONS Unless noted, timing and levels comply with MIPI DPHY standards. Table 2. DSI High Speed (HS) Specifications ADV7533 Parameters Symbol Temp Test Level Min Typ Max Unit DC SPECIFICATIONS DSI Input Common Mode Voltage VCMRX 25°C VII 70 330 mV DSI Input High Threshold VIDTH 25°C VII 70 mV DSI Input Low Threshold VIDTL 25°C VII −70 mV DSI Single-Ended Input High Voltage VIHHS 25°C VII 460 mV DSI Single-Ended Input Low Voltage VILHS 25°C VII −40 mV DSI Single-Ended Threshold for Termination Enable VTERM-EN 25°C VII 450 mV Differential Input Impedance ZID 25°C VII 80 100 125 Ω AC SPECIFICATIONS Single Channel Data Rate 25°C IV 200 800 Mbps Data to Clock Setup Time tSETUP 25°C VII 0.15 UIINST Data to Clock Hold Time tHOLD 25°C VII 0.15 UIINST DSI Clock Duty Cycle 25°C VII 45 50 55 % Common-Mode Interference Beyond 450 MHz ∆VCMRX(HF) 25°C VII 100 mV Common-Mode Interference 50 MHz to 450 MHz ∆VCMRX(LF) 25°C VII −50 +50 mV Common-Mode Termination CCM 25°C VII 60 pF |
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