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ADMP441ACEZ-RL7 bảng dữ liệu(PDF) 6 Page - Analog Devices

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ADMP441ACEZ-RL7 bảng dữ liệu(HTML) 6 Page - Analog Devices

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ADMP441
Data Sheet
Rev. A | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
4
L/R
6 GND
3
WS
7 VDD
2
SD
8 CHIPEN
1
SCK
9 GND
BOTTOM VIEW
(Not to Scale)
ADMP441
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Type
Description
1
SCK
Input
Serial Data Clock for I²S Interface.
2
SD
Output
Serial Data Output for I²S Interface. This pin tristates when not actively driving the appropriate
output channel. The SD trace should have a 100 kΩ pull-down resistor to discharge the line during
the time that all microphones on the bus have tristated their outputs.
3
WS
Input
Serial Data-Word Select for I²S Interface.
4
L/R
Input
Left/Right Channel Select. When set low, the microphone outputs its signal in the left channel of
the I²S frame; when set high, the microphone outputs its signal in the right channel.
5
GND
Ground
Ground. Connect to ground on the PCB.
6
GND
Ground
Ground. Connect to ground on the PCB.
7
VDD
Power
Power, 1.8 to 3.3 V. This pin should be decoupled to Pin 6 with a 0.1 μF capacitor.
8
CHIPEN
Input
Microphone Enable. When set low (ground), the microphone is disabled and put in power-down
mode. When set high (VDD), the microphone is enabled.
9
GND
Ground
Ground. Connect to ground on the PCB.


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