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AD5695RBRUZ bảng dữ liệu(PDF) 6 Page - Analog Devices

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AD5696R/AD5695R/AD5694R
Data Sheet
Rev. 0 | Page 6 of 32
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. 1
Table 4.
Parameter2
Min
Max
Unit
Conditions/Comments
t1
2.5
µs
SCL cycle time
t2
0.6
µs
tHIGH, SCL high time
t3
1.3
µs
tLOW, SCL low time
t4
0.6
µs
tHD,STA, start/repeated start condition hold time
t5
100
ns
tSU,DAT, data setup time
t63
0
0.9
µs
tHD,DAT, data hold time
t7
0.6
µs
tSU,STA, setup time for repeated start
t8
0.6
µs
tSU,STO, stop condition setup time
t9
1.3
µs
tBUF, bus free time between a stop and a start condition
t10
0
300
ns
tR, rise time of SCL and SDA when receiving
t11
20 + 0.1CB4
300
ns
tF, fall time of SDA and SCL when transmitting/ receiving
t12
20
ns
LDAC pulse width
t13
400
ns
SCL rising edge to LDAC rising edge
CB4
400
pF
Capacitive load for each bus line
1
See Figure 2.
2
Guaranteed by design and characterization; not production tested.
3
A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of SCL’s
falling edge.
4
CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.
Figure 2. 2-Wire Serial Interface Timing Diagram
SCL
SDA
t1
t3
LDAC1
LDAC2
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
NOTES
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
t4
t6
t5
t7
t8
t2
t13
t4
t11
t10
t12
t12
t9


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